1 /*
2 * ASPEED SoC family
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11
12 #ifndef ASPEED_SOC_H
13 #define ASPEED_SOC_H
14
15 #include "hw/cpu/a15mpcore.h"
16 #include "hw/arm/armv7m.h"
17 #include "hw/intc/aspeed_vic.h"
18 #include "hw/misc/aspeed_scu.h"
19 #include "hw/adc/aspeed_adc.h"
20 #include "hw/misc/aspeed_sdmc.h"
21 #include "hw/misc/aspeed_xdma.h"
22 #include "hw/timer/aspeed_timer.h"
23 #include "hw/rtc/aspeed_rtc.h"
24 #include "hw/i2c/aspeed_i2c.h"
25 #include "hw/misc/aspeed_i3c.h"
26 #include "hw/ssi/aspeed_smc.h"
27 #include "hw/misc/aspeed_hace.h"
28 #include "hw/misc/aspeed_sbc.h"
29 #include "hw/watchdog/wdt_aspeed.h"
30 #include "hw/net/ftgmac100.h"
31 #include "target/arm/cpu.h"
32 #include "hw/gpio/aspeed_gpio.h"
33 #include "hw/sd/aspeed_sdhci.h"
34 #include "hw/usb/hcd-ehci.h"
35 #include "qom/object.h"
36 #include "hw/misc/aspeed_lpc.h"
37 #include "hw/misc/unimp.h"
38 #include "hw/misc/aspeed_peci.h"
39 #include "hw/fsi/aspeed_apb2opb.h"
40 #include "hw/char/serial.h"
41
42 #define ASPEED_SPIS_NUM 2
43 #define ASPEED_EHCIS_NUM 2
44 #define ASPEED_WDTS_NUM 4
45 #define ASPEED_CPUS_NUM 2
46 #define ASPEED_MACS_NUM 4
47 #define ASPEED_UARTS_NUM 13
48 #define ASPEED_JTAG_NUM 2
49
50 struct AspeedSoCState {
51 DeviceState parent;
52
53 MemoryRegion *memory;
54 MemoryRegion *dram_mr;
55 MemoryRegion dram_container;
56 MemoryRegion sram;
57 MemoryRegion spi_boot_container;
58 MemoryRegion spi_boot;
59 AspeedRtcState rtc;
60 AspeedTimerCtrlState timerctrl;
61 AspeedI2CState i2c;
62 AspeedI3CState i3c;
63 AspeedSCUState scu;
64 AspeedHACEState hace;
65 AspeedXDMAState xdma;
66 AspeedADCState adc;
67 AspeedSMCState fmc;
68 AspeedSMCState spi[ASPEED_SPIS_NUM];
69 EHCISysBusState ehci[ASPEED_EHCIS_NUM];
70 AspeedSBCState sbc;
71 MemoryRegion secsram;
72 UnimplementedDeviceState sbc_unimplemented;
73 AspeedSDMCState sdmc;
74 AspeedWDTState wdt[ASPEED_WDTS_NUM];
75 FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
76 AspeedMiiState mii[ASPEED_MACS_NUM];
77 AspeedGPIOState gpio;
78 AspeedGPIOState gpio_1_8v;
79 AspeedSDHCIState sdhci;
80 AspeedSDHCIState emmc;
81 AspeedLPCState lpc;
82 AspeedPECIState peci;
83 SerialMM uart[ASPEED_UARTS_NUM];
84 Clock *sysclk;
85 UnimplementedDeviceState iomem;
86 UnimplementedDeviceState video;
87 UnimplementedDeviceState emmc_boot_controller;
88 UnimplementedDeviceState dpmcu;
89 UnimplementedDeviceState pwm;
90 UnimplementedDeviceState espi;
91 UnimplementedDeviceState udc;
92 UnimplementedDeviceState sgpiom;
93 UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];
94 AspeedAPB2OPBState fsi[2];
95 };
96
97 #define TYPE_ASPEED_SOC "aspeed-soc"
98 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
99
100 struct Aspeed2400SoCState {
101 AspeedSoCState parent;
102
103 ARMCPU cpu[ASPEED_CPUS_NUM];
104 AspeedVICState vic;
105 };
106
107 #define TYPE_ASPEED2400_SOC "aspeed2400-soc"
108 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC)
109
110 struct Aspeed2600SoCState {
111 AspeedSoCState parent;
112
113 A15MPPrivState a7mpcore;
114 ARMCPU cpu[ASPEED_CPUS_NUM]; /* XXX belong to a7mpcore */
115 };
116
117 #define TYPE_ASPEED2600_SOC "aspeed2600-soc"
118 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC)
119
120 struct Aspeed10x0SoCState {
121 AspeedSoCState parent;
122
123 ARMv7MState armv7m;
124 };
125
126 #define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
127 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC)
128
129 struct AspeedSoCClass {
130 DeviceClass parent_class;
131
132 const char *name;
133 /** valid_cpu_types: NULL terminated array of a single CPU type. */
134 const char * const *valid_cpu_types;
135 uint32_t silicon_rev;
136 uint64_t sram_size;
137 uint64_t secsram_size;
138 int spis_num;
139 int ehcis_num;
140 int wdts_num;
141 int macs_num;
142 int uarts_num;
143 int uarts_base;
144 const int *irqmap;
145 const hwaddr *memmap;
146 uint32_t num_cpus;
147 qemu_irq (*get_irq)(AspeedSoCState *s, int dev);
148 };
149
150 const char *aspeed_soc_cpu_type(AspeedSoCClass *sc);
151
152 enum {
153 ASPEED_DEV_SPI_BOOT,
154 ASPEED_DEV_IOMEM,
155 ASPEED_DEV_UART0,
156 ASPEED_DEV_UART1,
157 ASPEED_DEV_UART2,
158 ASPEED_DEV_UART3,
159 ASPEED_DEV_UART4,
160 ASPEED_DEV_UART5,
161 ASPEED_DEV_UART6,
162 ASPEED_DEV_UART7,
163 ASPEED_DEV_UART8,
164 ASPEED_DEV_UART9,
165 ASPEED_DEV_UART10,
166 ASPEED_DEV_UART11,
167 ASPEED_DEV_UART12,
168 ASPEED_DEV_UART13,
169 ASPEED_DEV_VUART,
170 ASPEED_DEV_FMC,
171 ASPEED_DEV_SPI1,
172 ASPEED_DEV_SPI2,
173 ASPEED_DEV_EHCI1,
174 ASPEED_DEV_EHCI2,
175 ASPEED_DEV_VIC,
176 ASPEED_DEV_SDMC,
177 ASPEED_DEV_SCU,
178 ASPEED_DEV_ADC,
179 ASPEED_DEV_SBC,
180 ASPEED_DEV_SECSRAM,
181 ASPEED_DEV_EMMC_BC,
182 ASPEED_DEV_VIDEO,
183 ASPEED_DEV_SRAM,
184 ASPEED_DEV_SDHCI,
185 ASPEED_DEV_GPIO,
186 ASPEED_DEV_GPIO_1_8V,
187 ASPEED_DEV_RTC,
188 ASPEED_DEV_TIMER1,
189 ASPEED_DEV_TIMER2,
190 ASPEED_DEV_TIMER3,
191 ASPEED_DEV_TIMER4,
192 ASPEED_DEV_TIMER5,
193 ASPEED_DEV_TIMER6,
194 ASPEED_DEV_TIMER7,
195 ASPEED_DEV_TIMER8,
196 ASPEED_DEV_WDT,
197 ASPEED_DEV_PWM,
198 ASPEED_DEV_LPC,
199 ASPEED_DEV_IBT,
200 ASPEED_DEV_I2C,
201 ASPEED_DEV_PECI,
202 ASPEED_DEV_ETH1,
203 ASPEED_DEV_ETH2,
204 ASPEED_DEV_ETH3,
205 ASPEED_DEV_ETH4,
206 ASPEED_DEV_MII1,
207 ASPEED_DEV_MII2,
208 ASPEED_DEV_MII3,
209 ASPEED_DEV_MII4,
210 ASPEED_DEV_SDRAM,
211 ASPEED_DEV_XDMA,
212 ASPEED_DEV_EMMC,
213 ASPEED_DEV_KCS,
214 ASPEED_DEV_HACE,
215 ASPEED_DEV_DPMCU,
216 ASPEED_DEV_DP,
217 ASPEED_DEV_I3C,
218 ASPEED_DEV_ESPI,
219 ASPEED_DEV_UDC,
220 ASPEED_DEV_SGPIOM,
221 ASPEED_DEV_JTAG0,
222 ASPEED_DEV_JTAG1,
223 ASPEED_DEV_FSI1,
224 ASPEED_DEV_FSI2,
225 };
226
227 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev);
228 bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp);
229 void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr);
230 bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp);
231 void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr);
232 void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
233 const char *name, hwaddr addr,
234 uint64_t size);
235 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
236 unsigned int count, int unit0);
237
aspeed_uart_index(int uart_dev)238 static inline int aspeed_uart_index(int uart_dev)
239 {
240 return uart_dev - ASPEED_DEV_UART0;
241 }
242
aspeed_uart_first(AspeedSoCClass * sc)243 static inline int aspeed_uart_first(AspeedSoCClass *sc)
244 {
245 return aspeed_uart_index(sc->uarts_base);
246 }
247
aspeed_uart_last(AspeedSoCClass * sc)248 static inline int aspeed_uart_last(AspeedSoCClass *sc)
249 {
250 return aspeed_uart_first(sc) + sc->uarts_num - 1;
251 }
252
253 #endif /* ASPEED_SOC_H */
254