1 /* 2 * ASPEED SoC family 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #ifndef ASPEED_SOC_H 13 #define ASPEED_SOC_H 14 15 #include "hw/cpu/a15mpcore.h" 16 #include "hw/arm/armv7m.h" 17 #include "hw/intc/aspeed_vic.h" 18 #include "hw/misc/aspeed_scu.h" 19 #include "hw/adc/aspeed_adc.h" 20 #include "hw/misc/aspeed_sdmc.h" 21 #include "hw/misc/aspeed_xdma.h" 22 #include "hw/timer/aspeed_timer.h" 23 #include "hw/rtc/aspeed_rtc.h" 24 #include "hw/i2c/aspeed_i2c.h" 25 #include "hw/misc/aspeed_i3c.h" 26 #include "hw/ssi/aspeed_smc.h" 27 #include "hw/misc/aspeed_hace.h" 28 #include "hw/misc/aspeed_sbc.h" 29 #include "hw/watchdog/wdt_aspeed.h" 30 #include "hw/net/ftgmac100.h" 31 #include "target/arm/cpu.h" 32 #include "hw/gpio/aspeed_gpio.h" 33 #include "hw/sd/aspeed_sdhci.h" 34 #include "hw/usb/hcd-ehci.h" 35 #include "qom/object.h" 36 #include "hw/misc/aspeed_lpc.h" 37 #include "hw/misc/unimp.h" 38 #include "hw/misc/aspeed_peci.h" 39 #include "hw/char/serial.h" 40 41 #define ASPEED_SPIS_NUM 2 42 #define ASPEED_EHCIS_NUM 2 43 #define ASPEED_WDTS_NUM 4 44 #define ASPEED_CPUS_NUM 2 45 #define ASPEED_MACS_NUM 4 46 #define ASPEED_UARTS_NUM 13 47 #define ASPEED_JTAG_NUM 2 48 49 struct AspeedSoCState { 50 DeviceState parent; 51 52 ARMCPU cpu[ASPEED_CPUS_NUM]; 53 A15MPPrivState a7mpcore; 54 MemoryRegion *memory; 55 MemoryRegion *dram_mr; 56 MemoryRegion dram_container; 57 MemoryRegion sram; 58 MemoryRegion spi_boot_container; 59 MemoryRegion spi_boot; 60 AspeedVICState vic; 61 AspeedRtcState rtc; 62 AspeedTimerCtrlState timerctrl; 63 AspeedI2CState i2c; 64 AspeedI3CState i3c; 65 AspeedSCUState scu; 66 AspeedHACEState hace; 67 AspeedXDMAState xdma; 68 AspeedADCState adc; 69 AspeedSMCState fmc; 70 AspeedSMCState spi[ASPEED_SPIS_NUM]; 71 EHCISysBusState ehci[ASPEED_EHCIS_NUM]; 72 AspeedSBCState sbc; 73 MemoryRegion secsram; 74 UnimplementedDeviceState sbc_unimplemented; 75 AspeedSDMCState sdmc; 76 AspeedWDTState wdt[ASPEED_WDTS_NUM]; 77 FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; 78 AspeedMiiState mii[ASPEED_MACS_NUM]; 79 AspeedGPIOState gpio; 80 AspeedGPIOState gpio_1_8v; 81 AspeedSDHCIState sdhci; 82 AspeedSDHCIState emmc; 83 AspeedLPCState lpc; 84 AspeedPECIState peci; 85 SerialMM uart[ASPEED_UARTS_NUM]; 86 Clock *sysclk; 87 UnimplementedDeviceState iomem; 88 UnimplementedDeviceState video; 89 UnimplementedDeviceState emmc_boot_controller; 90 UnimplementedDeviceState dpmcu; 91 UnimplementedDeviceState pwm; 92 UnimplementedDeviceState espi; 93 UnimplementedDeviceState udc; 94 UnimplementedDeviceState sgpiom; 95 UnimplementedDeviceState jtag[ASPEED_JTAG_NUM]; 96 }; 97 98 #define TYPE_ASPEED_SOC "aspeed-soc" 99 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC) 100 101 struct Aspeed2400SoCState { 102 AspeedSoCState parent; 103 }; 104 105 #define TYPE_ASPEED2400_SOC "aspeed2400-soc" 106 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC) 107 108 struct Aspeed2600SoCState { 109 AspeedSoCState parent; 110 }; 111 112 #define TYPE_ASPEED2600_SOC "aspeed2600-soc" 113 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC) 114 115 struct Aspeed10x0SoCState { 116 AspeedSoCState parent; 117 118 ARMv7MState armv7m; 119 }; 120 121 #define TYPE_ASPEED10X0_SOC "aspeed10x0-soc" 122 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC) 123 124 struct AspeedSoCClass { 125 DeviceClass parent_class; 126 127 const char *name; 128 const char *cpu_type; 129 uint32_t silicon_rev; 130 uint64_t sram_size; 131 uint64_t secsram_size; 132 int spis_num; 133 int ehcis_num; 134 int wdts_num; 135 int macs_num; 136 int uarts_num; 137 const int *irqmap; 138 const hwaddr *memmap; 139 uint32_t num_cpus; 140 qemu_irq (*get_irq)(AspeedSoCState *s, int dev); 141 }; 142 143 144 enum { 145 ASPEED_DEV_SPI_BOOT, 146 ASPEED_DEV_IOMEM, 147 ASPEED_DEV_UART1, 148 ASPEED_DEV_UART2, 149 ASPEED_DEV_UART3, 150 ASPEED_DEV_UART4, 151 ASPEED_DEV_UART5, 152 ASPEED_DEV_UART6, 153 ASPEED_DEV_UART7, 154 ASPEED_DEV_UART8, 155 ASPEED_DEV_UART9, 156 ASPEED_DEV_UART10, 157 ASPEED_DEV_UART11, 158 ASPEED_DEV_UART12, 159 ASPEED_DEV_UART13, 160 ASPEED_DEV_VUART, 161 ASPEED_DEV_FMC, 162 ASPEED_DEV_SPI1, 163 ASPEED_DEV_SPI2, 164 ASPEED_DEV_EHCI1, 165 ASPEED_DEV_EHCI2, 166 ASPEED_DEV_VIC, 167 ASPEED_DEV_SDMC, 168 ASPEED_DEV_SCU, 169 ASPEED_DEV_ADC, 170 ASPEED_DEV_SBC, 171 ASPEED_DEV_SECSRAM, 172 ASPEED_DEV_EMMC_BC, 173 ASPEED_DEV_VIDEO, 174 ASPEED_DEV_SRAM, 175 ASPEED_DEV_SDHCI, 176 ASPEED_DEV_GPIO, 177 ASPEED_DEV_GPIO_1_8V, 178 ASPEED_DEV_RTC, 179 ASPEED_DEV_TIMER1, 180 ASPEED_DEV_TIMER2, 181 ASPEED_DEV_TIMER3, 182 ASPEED_DEV_TIMER4, 183 ASPEED_DEV_TIMER5, 184 ASPEED_DEV_TIMER6, 185 ASPEED_DEV_TIMER7, 186 ASPEED_DEV_TIMER8, 187 ASPEED_DEV_WDT, 188 ASPEED_DEV_PWM, 189 ASPEED_DEV_LPC, 190 ASPEED_DEV_IBT, 191 ASPEED_DEV_I2C, 192 ASPEED_DEV_PECI, 193 ASPEED_DEV_ETH1, 194 ASPEED_DEV_ETH2, 195 ASPEED_DEV_ETH3, 196 ASPEED_DEV_ETH4, 197 ASPEED_DEV_MII1, 198 ASPEED_DEV_MII2, 199 ASPEED_DEV_MII3, 200 ASPEED_DEV_MII4, 201 ASPEED_DEV_SDRAM, 202 ASPEED_DEV_XDMA, 203 ASPEED_DEV_EMMC, 204 ASPEED_DEV_KCS, 205 ASPEED_DEV_HACE, 206 ASPEED_DEV_DPMCU, 207 ASPEED_DEV_DP, 208 ASPEED_DEV_I3C, 209 ASPEED_DEV_ESPI, 210 ASPEED_DEV_UDC, 211 ASPEED_DEV_SGPIOM, 212 ASPEED_DEV_JTAG0, 213 ASPEED_DEV_JTAG1, 214 }; 215 216 #define ASPEED_SOC_SPI_BOOT_ADDR 0x0 217 218 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev); 219 bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp); 220 void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr); 221 bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp); 222 void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr); 223 void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev, 224 const char *name, hwaddr addr, 225 uint64_t size); 226 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 227 unsigned int count, int unit0); 228 229 #endif /* ASPEED_SOC_H */ 230