1 /* 2 * ASPEED SoC family 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #ifndef ASPEED_SOC_H 13 #define ASPEED_SOC_H 14 15 #include "hw/cpu/a15mpcore.h" 16 #include "hw/arm/armv7m.h" 17 #include "hw/intc/aspeed_vic.h" 18 #include "hw/misc/aspeed_scu.h" 19 #include "hw/adc/aspeed_adc.h" 20 #include "hw/misc/aspeed_sdmc.h" 21 #include "hw/misc/aspeed_xdma.h" 22 #include "hw/timer/aspeed_timer.h" 23 #include "hw/rtc/aspeed_rtc.h" 24 #include "hw/i2c/aspeed_i2c.h" 25 #include "hw/misc/aspeed_i3c.h" 26 #include "hw/ssi/aspeed_smc.h" 27 #include "hw/misc/aspeed_hace.h" 28 #include "hw/misc/aspeed_sbc.h" 29 #include "hw/watchdog/wdt_aspeed.h" 30 #include "hw/net/ftgmac100.h" 31 #include "target/arm/cpu.h" 32 #include "hw/gpio/aspeed_gpio.h" 33 #include "hw/sd/aspeed_sdhci.h" 34 #include "hw/usb/hcd-ehci.h" 35 #include "qom/object.h" 36 #include "hw/misc/aspeed_lpc.h" 37 38 #define ASPEED_SPIS_NUM 2 39 #define ASPEED_EHCIS_NUM 2 40 #define ASPEED_WDTS_NUM 4 41 #define ASPEED_CPUS_NUM 2 42 #define ASPEED_MACS_NUM 4 43 44 struct AspeedSoCState { 45 /*< private >*/ 46 DeviceState parent; 47 48 /*< public >*/ 49 ARMCPU cpu[ASPEED_CPUS_NUM]; 50 A15MPPrivState a7mpcore; 51 ARMv7MState armv7m; 52 MemoryRegion *dram_mr; 53 MemoryRegion sram; 54 AspeedVICState vic; 55 AspeedRtcState rtc; 56 AspeedTimerCtrlState timerctrl; 57 AspeedI2CState i2c; 58 AspeedI3CState i3c; 59 AspeedSCUState scu; 60 AspeedHACEState hace; 61 AspeedXDMAState xdma; 62 AspeedADCState adc; 63 AspeedSMCState fmc; 64 AspeedSMCState spi[ASPEED_SPIS_NUM]; 65 EHCISysBusState ehci[ASPEED_EHCIS_NUM]; 66 AspeedSBCState sbc; 67 AspeedSDMCState sdmc; 68 AspeedWDTState wdt[ASPEED_WDTS_NUM]; 69 FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; 70 AspeedMiiState mii[ASPEED_MACS_NUM]; 71 AspeedGPIOState gpio; 72 AspeedGPIOState gpio_1_8v; 73 AspeedSDHCIState sdhci; 74 AspeedSDHCIState emmc; 75 AspeedLPCState lpc; 76 uint32_t uart_default; 77 Clock *sysclk; 78 }; 79 80 #define TYPE_ASPEED_SOC "aspeed-soc" 81 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC) 82 83 struct AspeedSoCClass { 84 DeviceClass parent_class; 85 86 const char *name; 87 const char *cpu_type; 88 uint32_t silicon_rev; 89 uint64_t sram_size; 90 int spis_num; 91 int ehcis_num; 92 int wdts_num; 93 int macs_num; 94 const int *irqmap; 95 const hwaddr *memmap; 96 uint32_t num_cpus; 97 }; 98 99 100 enum { 101 ASPEED_DEV_IOMEM, 102 ASPEED_DEV_UART1, 103 ASPEED_DEV_UART2, 104 ASPEED_DEV_UART3, 105 ASPEED_DEV_UART4, 106 ASPEED_DEV_UART5, 107 ASPEED_DEV_VUART, 108 ASPEED_DEV_FMC, 109 ASPEED_DEV_SPI1, 110 ASPEED_DEV_SPI2, 111 ASPEED_DEV_EHCI1, 112 ASPEED_DEV_EHCI2, 113 ASPEED_DEV_VIC, 114 ASPEED_DEV_SDMC, 115 ASPEED_DEV_SCU, 116 ASPEED_DEV_ADC, 117 ASPEED_DEV_SBC, 118 ASPEED_DEV_EMMC_BC, 119 ASPEED_DEV_VIDEO, 120 ASPEED_DEV_SRAM, 121 ASPEED_DEV_SDHCI, 122 ASPEED_DEV_GPIO, 123 ASPEED_DEV_GPIO_1_8V, 124 ASPEED_DEV_RTC, 125 ASPEED_DEV_TIMER1, 126 ASPEED_DEV_TIMER2, 127 ASPEED_DEV_TIMER3, 128 ASPEED_DEV_TIMER4, 129 ASPEED_DEV_TIMER5, 130 ASPEED_DEV_TIMER6, 131 ASPEED_DEV_TIMER7, 132 ASPEED_DEV_TIMER8, 133 ASPEED_DEV_WDT, 134 ASPEED_DEV_PWM, 135 ASPEED_DEV_LPC, 136 ASPEED_DEV_IBT, 137 ASPEED_DEV_I2C, 138 ASPEED_DEV_ETH1, 139 ASPEED_DEV_ETH2, 140 ASPEED_DEV_ETH3, 141 ASPEED_DEV_ETH4, 142 ASPEED_DEV_MII1, 143 ASPEED_DEV_MII2, 144 ASPEED_DEV_MII3, 145 ASPEED_DEV_MII4, 146 ASPEED_DEV_SDRAM, 147 ASPEED_DEV_XDMA, 148 ASPEED_DEV_EMMC, 149 ASPEED_DEV_KCS, 150 ASPEED_DEV_HACE, 151 ASPEED_DEV_DPMCU, 152 ASPEED_DEV_DP, 153 ASPEED_DEV_I3C, 154 }; 155 156 #endif /* ASPEED_SOC_H */ 157