104331d0bSMichael Clark /* 25b558380SMichael Clark * QEMU RISC-V VirtIO machine interface 304331d0bSMichael Clark * 404331d0bSMichael Clark * Copyright (c) 2017 SiFive, Inc. 504331d0bSMichael Clark * 604331d0bSMichael Clark * This program is free software; you can redistribute it and/or modify it 704331d0bSMichael Clark * under the terms and conditions of the GNU General Public License, 804331d0bSMichael Clark * version 2 or later, as published by the Free Software Foundation. 904331d0bSMichael Clark * 1004331d0bSMichael Clark * This program is distributed in the hope it will be useful, but WITHOUT 1104331d0bSMichael Clark * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1204331d0bSMichael Clark * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1304331d0bSMichael Clark * more details. 1404331d0bSMichael Clark * 1504331d0bSMichael Clark * You should have received a copy of the GNU General Public License along with 1604331d0bSMichael Clark * this program. If not, see <http://www.gnu.org/licenses/>. 1704331d0bSMichael Clark */ 1804331d0bSMichael Clark 194996b128SMichael Clark #ifndef HW_RISCV_VIRT_H 204996b128SMichael Clark #define HW_RISCV_VIRT_H 2104331d0bSMichael Clark 227a5951f6SMarkus Armbruster #include "hw/boards.h" 23ec150c7eSMarkus Armbruster #include "hw/riscv/riscv_hart.h" 24ec150c7eSMarkus Armbruster #include "hw/sysbus.h" 2571eb522cSAlistair Francis #include "hw/block/flash.h" 2668c8b403SSunil V L #include "hw/intc/riscv_imsic.h" 27ec150c7eSMarkus Armbruster 280631aaaeSAnup Patel #define VIRT_CPUS_MAX_BITS 9 2928d8c281SAnup Patel #define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS) 3028d8c281SAnup Patel #define VIRT_SOCKETS_MAX_BITS 2 3128d8c281SAnup Patel #define VIRT_SOCKETS_MAX (1 << VIRT_SOCKETS_MAX_BITS) 3218df0b46SAnup Patel 33cdfc19e4SAlistair Francis #define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt") 34db1015e9SEduardo Habkost typedef struct RISCVVirtState RISCVVirtState; 358110fa1dSEduardo Habkost DECLARE_INSTANCE_CHECKER(RISCVVirtState, RISCV_VIRT_MACHINE, 368110fa1dSEduardo Habkost TYPE_RISCV_VIRT_MACHINE) 37cdfc19e4SAlistair Francis 38e6faee65SAnup Patel typedef enum RISCVVirtAIAType { 39e6faee65SAnup Patel VIRT_AIA_TYPE_NONE = 0, 40e6faee65SAnup Patel VIRT_AIA_TYPE_APLIC, 4128d8c281SAnup Patel VIRT_AIA_TYPE_APLIC_IMSIC, 42e6faee65SAnup Patel } RISCVVirtAIAType; 43e6faee65SAnup Patel 44db1015e9SEduardo Habkost struct RISCVVirtState { 4504331d0bSMichael Clark /*< private >*/ 46cdfc19e4SAlistair Francis MachineState parent; 4704331d0bSMichael Clark 4804331d0bSMichael Clark /*< public >*/ 491c20d3ffSAlistair Francis Notifier machine_done; 501832b7cbSAlistair Francis DeviceState *platform_bus_dev; 5118df0b46SAnup Patel RISCVHartArrayState soc[VIRT_SOCKETS_MAX]; 52e6faee65SAnup Patel DeviceState *irqchip[VIRT_SOCKETS_MAX]; 5371eb522cSAlistair Francis PFlashCFI01 *flash[2]; 540489348dSAsherah Connor FWCfgState *fw_cfg; 55cdfc19e4SAlistair Francis 5604331d0bSMichael Clark int fdt_size; 57954886eaSAnup Patel bool have_aclint; 58e6faee65SAnup Patel RISCVVirtAIAType aia_type; 5928d8c281SAnup Patel int aia_guests; 6090477a65SSunil V L char *oem_id; 6190477a65SSunil V L char *oem_table_id; 62168b8c29SSunil V L OnOffAuto acpi; 6371302ff3SSunil V L const MemMapEntry *memmap; 64e86e9527SSunil V L struct GPEXHost *gpex_host; 65db1015e9SEduardo Habkost }; 6604331d0bSMichael Clark 6704331d0bSMichael Clark enum { 6804331d0bSMichael Clark VIRT_DEBUG, 6904331d0bSMichael Clark VIRT_MROM, 7004331d0bSMichael Clark VIRT_TEST, 7167b5ef30SAnup Patel VIRT_RTC, 7204331d0bSMichael Clark VIRT_CLINT, 73954886eaSAnup Patel VIRT_ACLINT_SSWI, 7404331d0bSMichael Clark VIRT_PLIC, 75e6faee65SAnup Patel VIRT_APLIC_M, 76e6faee65SAnup Patel VIRT_APLIC_S, 7704331d0bSMichael Clark VIRT_UART0, 7804331d0bSMichael Clark VIRT_VIRTIO, 790489348dSAsherah Connor VIRT_FW_CFG, 8028d8c281SAnup Patel VIRT_IMSIC_M, 8128d8c281SAnup Patel VIRT_IMSIC_S, 8271eb522cSAlistair Francis VIRT_FLASH, 836d56e396SAlistair Francis VIRT_DRAM, 846d56e396SAlistair Francis VIRT_PCIE_MMIO, 856d56e396SAlistair Francis VIRT_PCIE_PIO, 861832b7cbSAlistair Francis VIRT_PLATFORM_BUS, 876d56e396SAlistair Francis VIRT_PCIE_ECAM 8804331d0bSMichael Clark }; 8904331d0bSMichael Clark 9004331d0bSMichael Clark enum { 9104331d0bSMichael Clark UART0_IRQ = 10, 9267b5ef30SAnup Patel RTC_IRQ = 11, 9304331d0bSMichael Clark VIRTIO_IRQ = 1, /* 1 to 8 */ 9404331d0bSMichael Clark VIRTIO_COUNT = 8, 956d56e396SAlistair Francis PCIE_IRQ = 0x20, /* 32 to 35 */ 9659f74489SBin Meng VIRT_PLATFORM_BUS_IRQ = 64, /* 64 to 95 */ 9704331d0bSMichael Clark }; 9804331d0bSMichael Clark 991832b7cbSAlistair Francis #define VIRT_PLATFORM_BUS_NUM_IRQS 32 1001832b7cbSAlistair Francis 10128d8c281SAnup Patel #define VIRT_IRQCHIP_NUM_MSIS 255 10259f74489SBin Meng #define VIRT_IRQCHIP_NUM_SOURCES 96 103e6faee65SAnup Patel #define VIRT_IRQCHIP_NUM_PRIO_BITS 3 10428d8c281SAnup Patel #define VIRT_IRQCHIP_MAX_GUESTS_BITS 3 10528d8c281SAnup Patel #define VIRT_IRQCHIP_MAX_GUESTS ((1U << VIRT_IRQCHIP_MAX_GUESTS_BITS) - 1U) 106e6faee65SAnup Patel 1075decd2c5SBin Meng #define VIRT_PLIC_PRIORITY_BASE 0x00 10804331d0bSMichael Clark #define VIRT_PLIC_PENDING_BASE 0x1000 10904331d0bSMichael Clark #define VIRT_PLIC_ENABLE_BASE 0x2000 11004331d0bSMichael Clark #define VIRT_PLIC_ENABLE_STRIDE 0x80 11104331d0bSMichael Clark #define VIRT_PLIC_CONTEXT_BASE 0x200000 11204331d0bSMichael Clark #define VIRT_PLIC_CONTEXT_STRIDE 0x1000 11318df0b46SAnup Patel #define VIRT_PLIC_SIZE(__num_context) \ 11418df0b46SAnup Patel (VIRT_PLIC_CONTEXT_BASE + (__num_context) * VIRT_PLIC_CONTEXT_STRIDE) 11504331d0bSMichael Clark 1166d56e396SAlistair Francis #define FDT_PCI_ADDR_CELLS 3 1176d56e396SAlistair Francis #define FDT_PCI_INT_CELLS 1 11895e401d3SConor Dooley #define FDT_PLIC_ADDR_CELLS 0 1196d56e396SAlistair Francis #define FDT_PLIC_INT_CELLS 1 120e6faee65SAnup Patel #define FDT_APLIC_INT_CELLS 2 12128d8c281SAnup Patel #define FDT_IMSIC_INT_CELLS 0 122e6faee65SAnup Patel #define FDT_MAX_INT_CELLS 2 123e6faee65SAnup Patel #define FDT_MAX_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ 124e6faee65SAnup Patel 1 + FDT_MAX_INT_CELLS) 125e6faee65SAnup Patel #define FDT_PLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ 126e6faee65SAnup Patel 1 + FDT_PLIC_INT_CELLS) 127e6faee65SAnup Patel #define FDT_APLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ 128e6faee65SAnup Patel 1 + FDT_APLIC_INT_CELLS) 1296d56e396SAlistair Francis 130168b8c29SSunil V L bool virt_is_acpi_enabled(RISCVVirtState *s); 1317da2fb24SSunil V L void virt_acpi_setup(RISCVVirtState *vms); 13268c8b403SSunil V L uint32_t imsic_num_bits(uint32_t count); 13368c8b403SSunil V L 13468c8b403SSunil V L /* 13568c8b403SSunil V L * The virt machine physical address space used by some of the devices 13668c8b403SSunil V L * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets, 13768c8b403SSunil V L * number of CPUs, and number of IMSIC guest files. 13868c8b403SSunil V L * 13968c8b403SSunil V L * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS, 14068c8b403SSunil V L * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization 14168c8b403SSunil V L * of virt machine physical address space. 14268c8b403SSunil V L */ 14368c8b403SSunil V L 14468c8b403SSunil V L #define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT) 14568c8b403SSunil V L #if VIRT_IMSIC_GROUP_MAX_SIZE < \ 14668c8b403SSunil V L IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS) 147*b1470a14SManos Pitsidianakis #error "Can't accommodate single IMSIC group in address space" 14868c8b403SSunil V L #endif 14968c8b403SSunil V L 15068c8b403SSunil V L #define VIRT_IMSIC_MAX_SIZE (VIRT_SOCKETS_MAX * \ 15168c8b403SSunil V L VIRT_IMSIC_GROUP_MAX_SIZE) 15268c8b403SSunil V L #if 0x4000000 < VIRT_IMSIC_MAX_SIZE 153*b1470a14SManos Pitsidianakis #error "Can't accommodate all IMSIC groups in address space" 15468c8b403SSunil V L #endif 15568c8b403SSunil V L 15604331d0bSMichael Clark #endif 157