1*04331d0bSMichael Clark /* 2*04331d0bSMichael Clark * SiFive VirtIO Board 3*04331d0bSMichael Clark * 4*04331d0bSMichael Clark * Copyright (c) 2017 SiFive, Inc. 5*04331d0bSMichael Clark * 6*04331d0bSMichael Clark * This program is free software; you can redistribute it and/or modify it 7*04331d0bSMichael Clark * under the terms and conditions of the GNU General Public License, 8*04331d0bSMichael Clark * version 2 or later, as published by the Free Software Foundation. 9*04331d0bSMichael Clark * 10*04331d0bSMichael Clark * This program is distributed in the hope it will be useful, but WITHOUT 11*04331d0bSMichael Clark * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12*04331d0bSMichael Clark * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13*04331d0bSMichael Clark * more details. 14*04331d0bSMichael Clark * 15*04331d0bSMichael Clark * You should have received a copy of the GNU General Public License along with 16*04331d0bSMichael Clark * this program. If not, see <http://www.gnu.org/licenses/>. 17*04331d0bSMichael Clark */ 18*04331d0bSMichael Clark 19*04331d0bSMichael Clark #ifndef HW_VIRT_H 20*04331d0bSMichael Clark #define HW_VIRT_H 21*04331d0bSMichael Clark 22*04331d0bSMichael Clark #define TYPE_RISCV_VIRT_BOARD "riscv.virt" 23*04331d0bSMichael Clark #define VIRT(obj) \ 24*04331d0bSMichael Clark OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_BOARD) 25*04331d0bSMichael Clark 26*04331d0bSMichael Clark enum { ROM_BASE = 0x1000 }; 27*04331d0bSMichael Clark 28*04331d0bSMichael Clark typedef struct { 29*04331d0bSMichael Clark /*< private >*/ 30*04331d0bSMichael Clark SysBusDevice parent_obj; 31*04331d0bSMichael Clark 32*04331d0bSMichael Clark /*< public >*/ 33*04331d0bSMichael Clark RISCVHartArrayState soc; 34*04331d0bSMichael Clark DeviceState *plic; 35*04331d0bSMichael Clark void *fdt; 36*04331d0bSMichael Clark int fdt_size; 37*04331d0bSMichael Clark } RISCVVirtState; 38*04331d0bSMichael Clark 39*04331d0bSMichael Clark enum { 40*04331d0bSMichael Clark VIRT_DEBUG, 41*04331d0bSMichael Clark VIRT_MROM, 42*04331d0bSMichael Clark VIRT_TEST, 43*04331d0bSMichael Clark VIRT_CLINT, 44*04331d0bSMichael Clark VIRT_PLIC, 45*04331d0bSMichael Clark VIRT_UART0, 46*04331d0bSMichael Clark VIRT_VIRTIO, 47*04331d0bSMichael Clark VIRT_DRAM 48*04331d0bSMichael Clark }; 49*04331d0bSMichael Clark 50*04331d0bSMichael Clark 51*04331d0bSMichael Clark enum { 52*04331d0bSMichael Clark UART0_IRQ = 10, 53*04331d0bSMichael Clark VIRTIO_IRQ = 1, /* 1 to 8 */ 54*04331d0bSMichael Clark VIRTIO_COUNT = 8, 55*04331d0bSMichael Clark VIRTIO_NDEV = 10 56*04331d0bSMichael Clark }; 57*04331d0bSMichael Clark 58*04331d0bSMichael Clark #define VIRT_PLIC_HART_CONFIG "MS" 59*04331d0bSMichael Clark #define VIRT_PLIC_NUM_SOURCES 127 60*04331d0bSMichael Clark #define VIRT_PLIC_NUM_PRIORITIES 7 61*04331d0bSMichael Clark #define VIRT_PLIC_PRIORITY_BASE 0x0 62*04331d0bSMichael Clark #define VIRT_PLIC_PENDING_BASE 0x1000 63*04331d0bSMichael Clark #define VIRT_PLIC_ENABLE_BASE 0x2000 64*04331d0bSMichael Clark #define VIRT_PLIC_ENABLE_STRIDE 0x80 65*04331d0bSMichael Clark #define VIRT_PLIC_CONTEXT_BASE 0x200000 66*04331d0bSMichael Clark #define VIRT_PLIC_CONTEXT_STRIDE 0x1000 67*04331d0bSMichael Clark 68*04331d0bSMichael Clark #if defined(TARGET_RISCV32) 69*04331d0bSMichael Clark #define VIRT_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0 70*04331d0bSMichael Clark #elif defined(TARGET_RISCV64) 71*04331d0bSMichael Clark #define VIRT_CPU TYPE_RISCV_CPU_RV64GCSU_V1_10_0 72*04331d0bSMichael Clark #endif 73*04331d0bSMichael Clark 74*04331d0bSMichael Clark #endif 75