104331d0bSMichael Clark /* 25b558380SMichael Clark * QEMU RISC-V VirtIO machine interface 304331d0bSMichael Clark * 404331d0bSMichael Clark * Copyright (c) 2017 SiFive, Inc. 504331d0bSMichael Clark * 604331d0bSMichael Clark * This program is free software; you can redistribute it and/or modify it 704331d0bSMichael Clark * under the terms and conditions of the GNU General Public License, 804331d0bSMichael Clark * version 2 or later, as published by the Free Software Foundation. 904331d0bSMichael Clark * 1004331d0bSMichael Clark * This program is distributed in the hope it will be useful, but WITHOUT 1104331d0bSMichael Clark * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1204331d0bSMichael Clark * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1304331d0bSMichael Clark * more details. 1404331d0bSMichael Clark * 1504331d0bSMichael Clark * You should have received a copy of the GNU General Public License along with 1604331d0bSMichael Clark * this program. If not, see <http://www.gnu.org/licenses/>. 1704331d0bSMichael Clark */ 1804331d0bSMichael Clark 194996b128SMichael Clark #ifndef HW_RISCV_VIRT_H 204996b128SMichael Clark #define HW_RISCV_VIRT_H 2104331d0bSMichael Clark 22ec150c7eSMarkus Armbruster #include "hw/riscv/riscv_hart.h" 23ec150c7eSMarkus Armbruster #include "hw/sysbus.h" 2471eb522cSAlistair Francis #include "hw/block/flash.h" 25db1015e9SEduardo Habkost #include "qom/object.h" 26ec150c7eSMarkus Armbruster 2718df0b46SAnup Patel #define VIRT_CPUS_MAX 8 2818df0b46SAnup Patel #define VIRT_SOCKETS_MAX 8 2918df0b46SAnup Patel 30cdfc19e4SAlistair Francis #define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt") 31db1015e9SEduardo Habkost typedef struct RISCVVirtState RISCVVirtState; 328110fa1dSEduardo Habkost DECLARE_INSTANCE_CHECKER(RISCVVirtState, RISCV_VIRT_MACHINE, 338110fa1dSEduardo Habkost TYPE_RISCV_VIRT_MACHINE) 34cdfc19e4SAlistair Francis 35db1015e9SEduardo Habkost struct RISCVVirtState { 3604331d0bSMichael Clark /*< private >*/ 37cdfc19e4SAlistair Francis MachineState parent; 3804331d0bSMichael Clark 3904331d0bSMichael Clark /*< public >*/ 4018df0b46SAnup Patel RISCVHartArrayState soc[VIRT_SOCKETS_MAX]; 4118df0b46SAnup Patel DeviceState *plic[VIRT_SOCKETS_MAX]; 4271eb522cSAlistair Francis PFlashCFI01 *flash[2]; 43*0489348dSAsherah Connor FWCfgState *fw_cfg; 44cdfc19e4SAlistair Francis 4504331d0bSMichael Clark int fdt_size; 46db1015e9SEduardo Habkost }; 4704331d0bSMichael Clark 4804331d0bSMichael Clark enum { 4904331d0bSMichael Clark VIRT_DEBUG, 5004331d0bSMichael Clark VIRT_MROM, 5104331d0bSMichael Clark VIRT_TEST, 5267b5ef30SAnup Patel VIRT_RTC, 5304331d0bSMichael Clark VIRT_CLINT, 5404331d0bSMichael Clark VIRT_PLIC, 5504331d0bSMichael Clark VIRT_UART0, 5604331d0bSMichael Clark VIRT_VIRTIO, 57*0489348dSAsherah Connor VIRT_FW_CFG, 5871eb522cSAlistair Francis VIRT_FLASH, 596d56e396SAlistair Francis VIRT_DRAM, 606d56e396SAlistair Francis VIRT_PCIE_MMIO, 616d56e396SAlistair Francis VIRT_PCIE_PIO, 626d56e396SAlistair Francis VIRT_PCIE_ECAM 6304331d0bSMichael Clark }; 6404331d0bSMichael Clark 6504331d0bSMichael Clark enum { 6604331d0bSMichael Clark UART0_IRQ = 10, 6767b5ef30SAnup Patel RTC_IRQ = 11, 6804331d0bSMichael Clark VIRTIO_IRQ = 1, /* 1 to 8 */ 6904331d0bSMichael Clark VIRTIO_COUNT = 8, 706d56e396SAlistair Francis PCIE_IRQ = 0x20, /* 32 to 35 */ 7163b695f2SAlistair Francis VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */ 7204331d0bSMichael Clark }; 7304331d0bSMichael Clark 7404331d0bSMichael Clark #define VIRT_PLIC_HART_CONFIG "MS" 7504331d0bSMichael Clark #define VIRT_PLIC_NUM_SOURCES 127 7604331d0bSMichael Clark #define VIRT_PLIC_NUM_PRIORITIES 7 770feb4a71SAlistair Francis #define VIRT_PLIC_PRIORITY_BASE 0x04 7804331d0bSMichael Clark #define VIRT_PLIC_PENDING_BASE 0x1000 7904331d0bSMichael Clark #define VIRT_PLIC_ENABLE_BASE 0x2000 8004331d0bSMichael Clark #define VIRT_PLIC_ENABLE_STRIDE 0x80 8104331d0bSMichael Clark #define VIRT_PLIC_CONTEXT_BASE 0x200000 8204331d0bSMichael Clark #define VIRT_PLIC_CONTEXT_STRIDE 0x1000 8318df0b46SAnup Patel #define VIRT_PLIC_SIZE(__num_context) \ 8418df0b46SAnup Patel (VIRT_PLIC_CONTEXT_BASE + (__num_context) * VIRT_PLIC_CONTEXT_STRIDE) 8504331d0bSMichael Clark 866d56e396SAlistair Francis #define FDT_PCI_ADDR_CELLS 3 876d56e396SAlistair Francis #define FDT_PCI_INT_CELLS 1 886d56e396SAlistair Francis #define FDT_PLIC_ADDR_CELLS 0 896d56e396SAlistair Francis #define FDT_PLIC_INT_CELLS 1 906d56e396SAlistair Francis #define FDT_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + 1 + \ 916d56e396SAlistair Francis FDT_PLIC_ADDR_CELLS + FDT_PLIC_INT_CELLS) 926d56e396SAlistair Francis 9304331d0bSMichael Clark #endif 94