104331d0bSMichael Clark /* 25b558380SMichael Clark * QEMU RISC-V VirtIO machine interface 304331d0bSMichael Clark * 404331d0bSMichael Clark * Copyright (c) 2017 SiFive, Inc. 504331d0bSMichael Clark * 604331d0bSMichael Clark * This program is free software; you can redistribute it and/or modify it 704331d0bSMichael Clark * under the terms and conditions of the GNU General Public License, 804331d0bSMichael Clark * version 2 or later, as published by the Free Software Foundation. 904331d0bSMichael Clark * 1004331d0bSMichael Clark * This program is distributed in the hope it will be useful, but WITHOUT 1104331d0bSMichael Clark * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1204331d0bSMichael Clark * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1304331d0bSMichael Clark * more details. 1404331d0bSMichael Clark * 1504331d0bSMichael Clark * You should have received a copy of the GNU General Public License along with 1604331d0bSMichael Clark * this program. If not, see <http://www.gnu.org/licenses/>. 1704331d0bSMichael Clark */ 1804331d0bSMichael Clark 194996b128SMichael Clark #ifndef HW_RISCV_VIRT_H 204996b128SMichael Clark #define HW_RISCV_VIRT_H 2104331d0bSMichael Clark 22ec150c7eSMarkus Armbruster #include "hw/riscv/riscv_hart.h" 23ec150c7eSMarkus Armbruster #include "hw/sysbus.h" 2471eb522cSAlistair Francis #include "hw/block/flash.h" 25db1015e9SEduardo Habkost #include "qom/object.h" 26ec150c7eSMarkus Armbruster 27*0631aaaeSAnup Patel #define VIRT_CPUS_MAX_BITS 9 2828d8c281SAnup Patel #define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS) 2928d8c281SAnup Patel #define VIRT_SOCKETS_MAX_BITS 2 3028d8c281SAnup Patel #define VIRT_SOCKETS_MAX (1 << VIRT_SOCKETS_MAX_BITS) 3118df0b46SAnup Patel 32cdfc19e4SAlistair Francis #define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt") 33db1015e9SEduardo Habkost typedef struct RISCVVirtState RISCVVirtState; 348110fa1dSEduardo Habkost DECLARE_INSTANCE_CHECKER(RISCVVirtState, RISCV_VIRT_MACHINE, 358110fa1dSEduardo Habkost TYPE_RISCV_VIRT_MACHINE) 36cdfc19e4SAlistair Francis 37e6faee65SAnup Patel typedef enum RISCVVirtAIAType { 38e6faee65SAnup Patel VIRT_AIA_TYPE_NONE = 0, 39e6faee65SAnup Patel VIRT_AIA_TYPE_APLIC, 4028d8c281SAnup Patel VIRT_AIA_TYPE_APLIC_IMSIC, 41e6faee65SAnup Patel } RISCVVirtAIAType; 42e6faee65SAnup Patel 43db1015e9SEduardo Habkost struct RISCVVirtState { 4404331d0bSMichael Clark /*< private >*/ 45cdfc19e4SAlistair Francis MachineState parent; 4604331d0bSMichael Clark 4704331d0bSMichael Clark /*< public >*/ 4818df0b46SAnup Patel RISCVHartArrayState soc[VIRT_SOCKETS_MAX]; 49e6faee65SAnup Patel DeviceState *irqchip[VIRT_SOCKETS_MAX]; 5071eb522cSAlistair Francis PFlashCFI01 *flash[2]; 510489348dSAsherah Connor FWCfgState *fw_cfg; 52cdfc19e4SAlistair Francis 5304331d0bSMichael Clark int fdt_size; 54954886eaSAnup Patel bool have_aclint; 55e6faee65SAnup Patel RISCVVirtAIAType aia_type; 5628d8c281SAnup Patel int aia_guests; 57db1015e9SEduardo Habkost }; 5804331d0bSMichael Clark 5904331d0bSMichael Clark enum { 6004331d0bSMichael Clark VIRT_DEBUG, 6104331d0bSMichael Clark VIRT_MROM, 6204331d0bSMichael Clark VIRT_TEST, 6367b5ef30SAnup Patel VIRT_RTC, 6404331d0bSMichael Clark VIRT_CLINT, 65954886eaSAnup Patel VIRT_ACLINT_SSWI, 6604331d0bSMichael Clark VIRT_PLIC, 67e6faee65SAnup Patel VIRT_APLIC_M, 68e6faee65SAnup Patel VIRT_APLIC_S, 6904331d0bSMichael Clark VIRT_UART0, 7004331d0bSMichael Clark VIRT_VIRTIO, 710489348dSAsherah Connor VIRT_FW_CFG, 7228d8c281SAnup Patel VIRT_IMSIC_M, 7328d8c281SAnup Patel VIRT_IMSIC_S, 7471eb522cSAlistair Francis VIRT_FLASH, 756d56e396SAlistair Francis VIRT_DRAM, 766d56e396SAlistair Francis VIRT_PCIE_MMIO, 776d56e396SAlistair Francis VIRT_PCIE_PIO, 786d56e396SAlistair Francis VIRT_PCIE_ECAM 7904331d0bSMichael Clark }; 8004331d0bSMichael Clark 8104331d0bSMichael Clark enum { 8204331d0bSMichael Clark UART0_IRQ = 10, 8367b5ef30SAnup Patel RTC_IRQ = 11, 8404331d0bSMichael Clark VIRTIO_IRQ = 1, /* 1 to 8 */ 8504331d0bSMichael Clark VIRTIO_COUNT = 8, 866d56e396SAlistair Francis PCIE_IRQ = 0x20, /* 32 to 35 */ 8763b695f2SAlistair Francis VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */ 8804331d0bSMichael Clark }; 8904331d0bSMichael Clark 9028d8c281SAnup Patel #define VIRT_IRQCHIP_IPI_MSI 1 9128d8c281SAnup Patel #define VIRT_IRQCHIP_NUM_MSIS 255 9228d8c281SAnup Patel #define VIRT_IRQCHIP_NUM_SOURCES VIRTIO_NDEV 93e6faee65SAnup Patel #define VIRT_IRQCHIP_NUM_PRIO_BITS 3 9428d8c281SAnup Patel #define VIRT_IRQCHIP_MAX_GUESTS_BITS 3 9528d8c281SAnup Patel #define VIRT_IRQCHIP_MAX_GUESTS ((1U << VIRT_IRQCHIP_MAX_GUESTS_BITS) - 1U) 96e6faee65SAnup Patel 970feb4a71SAlistair Francis #define VIRT_PLIC_PRIORITY_BASE 0x04 9804331d0bSMichael Clark #define VIRT_PLIC_PENDING_BASE 0x1000 9904331d0bSMichael Clark #define VIRT_PLIC_ENABLE_BASE 0x2000 10004331d0bSMichael Clark #define VIRT_PLIC_ENABLE_STRIDE 0x80 10104331d0bSMichael Clark #define VIRT_PLIC_CONTEXT_BASE 0x200000 10204331d0bSMichael Clark #define VIRT_PLIC_CONTEXT_STRIDE 0x1000 10318df0b46SAnup Patel #define VIRT_PLIC_SIZE(__num_context) \ 10418df0b46SAnup Patel (VIRT_PLIC_CONTEXT_BASE + (__num_context) * VIRT_PLIC_CONTEXT_STRIDE) 10504331d0bSMichael Clark 1066d56e396SAlistair Francis #define FDT_PCI_ADDR_CELLS 3 1076d56e396SAlistair Francis #define FDT_PCI_INT_CELLS 1 1086d56e396SAlistair Francis #define FDT_PLIC_INT_CELLS 1 109e6faee65SAnup Patel #define FDT_APLIC_INT_CELLS 2 11028d8c281SAnup Patel #define FDT_IMSIC_INT_CELLS 0 111e6faee65SAnup Patel #define FDT_MAX_INT_CELLS 2 112e6faee65SAnup Patel #define FDT_MAX_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ 113e6faee65SAnup Patel 1 + FDT_MAX_INT_CELLS) 114e6faee65SAnup Patel #define FDT_PLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ 115e6faee65SAnup Patel 1 + FDT_PLIC_INT_CELLS) 116e6faee65SAnup Patel #define FDT_APLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ 117e6faee65SAnup Patel 1 + FDT_APLIC_INT_CELLS) 1186d56e396SAlistair Francis 11904331d0bSMichael Clark #endif 120