104331d0bSMichael Clark /* 2*5b558380SMichael Clark * QEMU RISC-V VirtIO machine interface 304331d0bSMichael Clark * 404331d0bSMichael Clark * Copyright (c) 2017 SiFive, Inc. 504331d0bSMichael Clark * 604331d0bSMichael Clark * This program is free software; you can redistribute it and/or modify it 704331d0bSMichael Clark * under the terms and conditions of the GNU General Public License, 804331d0bSMichael Clark * version 2 or later, as published by the Free Software Foundation. 904331d0bSMichael Clark * 1004331d0bSMichael Clark * This program is distributed in the hope it will be useful, but WITHOUT 1104331d0bSMichael Clark * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1204331d0bSMichael Clark * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1304331d0bSMichael Clark * more details. 1404331d0bSMichael Clark * 1504331d0bSMichael Clark * You should have received a copy of the GNU General Public License along with 1604331d0bSMichael Clark * this program. If not, see <http://www.gnu.org/licenses/>. 1704331d0bSMichael Clark */ 1804331d0bSMichael Clark 194996b128SMichael Clark #ifndef HW_RISCV_VIRT_H 204996b128SMichael Clark #define HW_RISCV_VIRT_H 2104331d0bSMichael Clark 2204331d0bSMichael Clark typedef struct { 2304331d0bSMichael Clark /*< private >*/ 2404331d0bSMichael Clark SysBusDevice parent_obj; 2504331d0bSMichael Clark 2604331d0bSMichael Clark /*< public >*/ 2704331d0bSMichael Clark RISCVHartArrayState soc; 2804331d0bSMichael Clark DeviceState *plic; 2904331d0bSMichael Clark void *fdt; 3004331d0bSMichael Clark int fdt_size; 3104331d0bSMichael Clark } RISCVVirtState; 3204331d0bSMichael Clark 3304331d0bSMichael Clark enum { 3404331d0bSMichael Clark VIRT_DEBUG, 3504331d0bSMichael Clark VIRT_MROM, 3604331d0bSMichael Clark VIRT_TEST, 3704331d0bSMichael Clark VIRT_CLINT, 3804331d0bSMichael Clark VIRT_PLIC, 3904331d0bSMichael Clark VIRT_UART0, 4004331d0bSMichael Clark VIRT_VIRTIO, 4104331d0bSMichael Clark VIRT_DRAM 4204331d0bSMichael Clark }; 4304331d0bSMichael Clark 4404331d0bSMichael Clark enum { 4504331d0bSMichael Clark UART0_IRQ = 10, 4604331d0bSMichael Clark VIRTIO_IRQ = 1, /* 1 to 8 */ 4704331d0bSMichael Clark VIRTIO_COUNT = 8, 4804331d0bSMichael Clark VIRTIO_NDEV = 10 4904331d0bSMichael Clark }; 5004331d0bSMichael Clark 512a8756edSMichael Clark enum { 522a8756edSMichael Clark VIRT_CLOCK_FREQ = 1000000000 532a8756edSMichael Clark }; 542a8756edSMichael Clark 5504331d0bSMichael Clark #define VIRT_PLIC_HART_CONFIG "MS" 5604331d0bSMichael Clark #define VIRT_PLIC_NUM_SOURCES 127 5704331d0bSMichael Clark #define VIRT_PLIC_NUM_PRIORITIES 7 5804331d0bSMichael Clark #define VIRT_PLIC_PRIORITY_BASE 0x0 5904331d0bSMichael Clark #define VIRT_PLIC_PENDING_BASE 0x1000 6004331d0bSMichael Clark #define VIRT_PLIC_ENABLE_BASE 0x2000 6104331d0bSMichael Clark #define VIRT_PLIC_ENABLE_STRIDE 0x80 6204331d0bSMichael Clark #define VIRT_PLIC_CONTEXT_BASE 0x200000 6304331d0bSMichael Clark #define VIRT_PLIC_CONTEXT_STRIDE 0x1000 6404331d0bSMichael Clark 6504331d0bSMichael Clark #if defined(TARGET_RISCV32) 6604331d0bSMichael Clark #define VIRT_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0 6704331d0bSMichael Clark #elif defined(TARGET_RISCV64) 6804331d0bSMichael Clark #define VIRT_CPU TYPE_RISCV_CPU_RV64GCSU_V1_10_0 6904331d0bSMichael Clark #endif 7004331d0bSMichael Clark 7104331d0bSMichael Clark #endif 72