104331d0bSMichael Clark /* 25b558380SMichael Clark * QEMU RISC-V VirtIO machine interface 304331d0bSMichael Clark * 404331d0bSMichael Clark * Copyright (c) 2017 SiFive, Inc. 504331d0bSMichael Clark * 604331d0bSMichael Clark * This program is free software; you can redistribute it and/or modify it 704331d0bSMichael Clark * under the terms and conditions of the GNU General Public License, 804331d0bSMichael Clark * version 2 or later, as published by the Free Software Foundation. 904331d0bSMichael Clark * 1004331d0bSMichael Clark * This program is distributed in the hope it will be useful, but WITHOUT 1104331d0bSMichael Clark * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1204331d0bSMichael Clark * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1304331d0bSMichael Clark * more details. 1404331d0bSMichael Clark * 1504331d0bSMichael Clark * You should have received a copy of the GNU General Public License along with 1604331d0bSMichael Clark * this program. If not, see <http://www.gnu.org/licenses/>. 1704331d0bSMichael Clark */ 1804331d0bSMichael Clark 194996b128SMichael Clark #ifndef HW_RISCV_VIRT_H 204996b128SMichael Clark #define HW_RISCV_VIRT_H 2104331d0bSMichael Clark 227a5951f6SMarkus Armbruster #include "hw/boards.h" 23ec150c7eSMarkus Armbruster #include "hw/riscv/riscv_hart.h" 24ec150c7eSMarkus Armbruster #include "hw/sysbus.h" 2571eb522cSAlistair Francis #include "hw/block/flash.h" 26ec150c7eSMarkus Armbruster 270631aaaeSAnup Patel #define VIRT_CPUS_MAX_BITS 9 2828d8c281SAnup Patel #define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS) 2928d8c281SAnup Patel #define VIRT_SOCKETS_MAX_BITS 2 3028d8c281SAnup Patel #define VIRT_SOCKETS_MAX (1 << VIRT_SOCKETS_MAX_BITS) 3118df0b46SAnup Patel 32cdfc19e4SAlistair Francis #define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt") 33db1015e9SEduardo Habkost typedef struct RISCVVirtState RISCVVirtState; 348110fa1dSEduardo Habkost DECLARE_INSTANCE_CHECKER(RISCVVirtState, RISCV_VIRT_MACHINE, 358110fa1dSEduardo Habkost TYPE_RISCV_VIRT_MACHINE) 36cdfc19e4SAlistair Francis 37e6faee65SAnup Patel typedef enum RISCVVirtAIAType { 38e6faee65SAnup Patel VIRT_AIA_TYPE_NONE = 0, 39e6faee65SAnup Patel VIRT_AIA_TYPE_APLIC, 4028d8c281SAnup Patel VIRT_AIA_TYPE_APLIC_IMSIC, 41e6faee65SAnup Patel } RISCVVirtAIAType; 42e6faee65SAnup Patel 43db1015e9SEduardo Habkost struct RISCVVirtState { 4404331d0bSMichael Clark /*< private >*/ 45cdfc19e4SAlistair Francis MachineState parent; 4604331d0bSMichael Clark 4704331d0bSMichael Clark /*< public >*/ 481c20d3ffSAlistair Francis Notifier machine_done; 491832b7cbSAlistair Francis DeviceState *platform_bus_dev; 5018df0b46SAnup Patel RISCVHartArrayState soc[VIRT_SOCKETS_MAX]; 51e6faee65SAnup Patel DeviceState *irqchip[VIRT_SOCKETS_MAX]; 5271eb522cSAlistair Francis PFlashCFI01 *flash[2]; 530489348dSAsherah Connor FWCfgState *fw_cfg; 54cdfc19e4SAlistair Francis 5504331d0bSMichael Clark int fdt_size; 56954886eaSAnup Patel bool have_aclint; 57e6faee65SAnup Patel RISCVVirtAIAType aia_type; 5828d8c281SAnup Patel int aia_guests; 5990477a65SSunil V L char *oem_id; 6090477a65SSunil V L char *oem_table_id; 61168b8c29SSunil V L OnOffAuto acpi; 6271302ff3SSunil V L const MemMapEntry *memmap; 63db1015e9SEduardo Habkost }; 6404331d0bSMichael Clark 6504331d0bSMichael Clark enum { 6604331d0bSMichael Clark VIRT_DEBUG, 6704331d0bSMichael Clark VIRT_MROM, 6804331d0bSMichael Clark VIRT_TEST, 6967b5ef30SAnup Patel VIRT_RTC, 7004331d0bSMichael Clark VIRT_CLINT, 71954886eaSAnup Patel VIRT_ACLINT_SSWI, 7204331d0bSMichael Clark VIRT_PLIC, 73e6faee65SAnup Patel VIRT_APLIC_M, 74e6faee65SAnup Patel VIRT_APLIC_S, 7504331d0bSMichael Clark VIRT_UART0, 7604331d0bSMichael Clark VIRT_VIRTIO, 770489348dSAsherah Connor VIRT_FW_CFG, 7828d8c281SAnup Patel VIRT_IMSIC_M, 7928d8c281SAnup Patel VIRT_IMSIC_S, 8071eb522cSAlistair Francis VIRT_FLASH, 816d56e396SAlistair Francis VIRT_DRAM, 826d56e396SAlistair Francis VIRT_PCIE_MMIO, 836d56e396SAlistair Francis VIRT_PCIE_PIO, 841832b7cbSAlistair Francis VIRT_PLATFORM_BUS, 856d56e396SAlistair Francis VIRT_PCIE_ECAM 8604331d0bSMichael Clark }; 8704331d0bSMichael Clark 8804331d0bSMichael Clark enum { 8904331d0bSMichael Clark UART0_IRQ = 10, 9067b5ef30SAnup Patel RTC_IRQ = 11, 9104331d0bSMichael Clark VIRTIO_IRQ = 1, /* 1 to 8 */ 9204331d0bSMichael Clark VIRTIO_COUNT = 8, 936d56e396SAlistair Francis PCIE_IRQ = 0x20, /* 32 to 35 */ 9459f74489SBin Meng VIRT_PLATFORM_BUS_IRQ = 64, /* 64 to 95 */ 9504331d0bSMichael Clark }; 9604331d0bSMichael Clark 971832b7cbSAlistair Francis #define VIRT_PLATFORM_BUS_NUM_IRQS 32 981832b7cbSAlistair Francis 9928d8c281SAnup Patel #define VIRT_IRQCHIP_NUM_MSIS 255 10059f74489SBin Meng #define VIRT_IRQCHIP_NUM_SOURCES 96 101e6faee65SAnup Patel #define VIRT_IRQCHIP_NUM_PRIO_BITS 3 10228d8c281SAnup Patel #define VIRT_IRQCHIP_MAX_GUESTS_BITS 3 10328d8c281SAnup Patel #define VIRT_IRQCHIP_MAX_GUESTS ((1U << VIRT_IRQCHIP_MAX_GUESTS_BITS) - 1U) 104e6faee65SAnup Patel 1055decd2c5SBin Meng #define VIRT_PLIC_PRIORITY_BASE 0x00 10604331d0bSMichael Clark #define VIRT_PLIC_PENDING_BASE 0x1000 10704331d0bSMichael Clark #define VIRT_PLIC_ENABLE_BASE 0x2000 10804331d0bSMichael Clark #define VIRT_PLIC_ENABLE_STRIDE 0x80 10904331d0bSMichael Clark #define VIRT_PLIC_CONTEXT_BASE 0x200000 11004331d0bSMichael Clark #define VIRT_PLIC_CONTEXT_STRIDE 0x1000 11118df0b46SAnup Patel #define VIRT_PLIC_SIZE(__num_context) \ 11218df0b46SAnup Patel (VIRT_PLIC_CONTEXT_BASE + (__num_context) * VIRT_PLIC_CONTEXT_STRIDE) 11304331d0bSMichael Clark 1146d56e396SAlistair Francis #define FDT_PCI_ADDR_CELLS 3 1156d56e396SAlistair Francis #define FDT_PCI_INT_CELLS 1 11695e401d3SConor Dooley #define FDT_PLIC_ADDR_CELLS 0 1176d56e396SAlistair Francis #define FDT_PLIC_INT_CELLS 1 118e6faee65SAnup Patel #define FDT_APLIC_INT_CELLS 2 11928d8c281SAnup Patel #define FDT_IMSIC_INT_CELLS 0 120e6faee65SAnup Patel #define FDT_MAX_INT_CELLS 2 121e6faee65SAnup Patel #define FDT_MAX_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ 122e6faee65SAnup Patel 1 + FDT_MAX_INT_CELLS) 123e6faee65SAnup Patel #define FDT_PLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ 124e6faee65SAnup Patel 1 + FDT_PLIC_INT_CELLS) 125e6faee65SAnup Patel #define FDT_APLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ 126e6faee65SAnup Patel 1 + FDT_APLIC_INT_CELLS) 1276d56e396SAlistair Francis 128168b8c29SSunil V L bool virt_is_acpi_enabled(RISCVVirtState *s); 1297da2fb24SSunil V L void virt_acpi_setup(RISCVVirtState *vms); 13004331d0bSMichael Clark #endif 131