104331d0bSMichael Clark /* 25b558380SMichael Clark * QEMU RISC-V VirtIO machine interface 304331d0bSMichael Clark * 404331d0bSMichael Clark * Copyright (c) 2017 SiFive, Inc. 504331d0bSMichael Clark * 604331d0bSMichael Clark * This program is free software; you can redistribute it and/or modify it 704331d0bSMichael Clark * under the terms and conditions of the GNU General Public License, 804331d0bSMichael Clark * version 2 or later, as published by the Free Software Foundation. 904331d0bSMichael Clark * 1004331d0bSMichael Clark * This program is distributed in the hope it will be useful, but WITHOUT 1104331d0bSMichael Clark * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1204331d0bSMichael Clark * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1304331d0bSMichael Clark * more details. 1404331d0bSMichael Clark * 1504331d0bSMichael Clark * You should have received a copy of the GNU General Public License along with 1604331d0bSMichael Clark * this program. If not, see <http://www.gnu.org/licenses/>. 1704331d0bSMichael Clark */ 1804331d0bSMichael Clark 194996b128SMichael Clark #ifndef HW_RISCV_VIRT_H 204996b128SMichael Clark #define HW_RISCV_VIRT_H 2104331d0bSMichael Clark 22ec150c7eSMarkus Armbruster #include "hw/riscv/riscv_hart.h" 23ec150c7eSMarkus Armbruster #include "hw/sysbus.h" 2471eb522cSAlistair Francis #include "hw/block/flash.h" 25db1015e9SEduardo Habkost #include "qom/object.h" 26ec150c7eSMarkus Armbruster 27d4452c69SAlistair Francis #define VIRT_CPUS_MAX 32 2818df0b46SAnup Patel #define VIRT_SOCKETS_MAX 8 2918df0b46SAnup Patel 30cdfc19e4SAlistair Francis #define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt") 31db1015e9SEduardo Habkost typedef struct RISCVVirtState RISCVVirtState; 328110fa1dSEduardo Habkost DECLARE_INSTANCE_CHECKER(RISCVVirtState, RISCV_VIRT_MACHINE, 338110fa1dSEduardo Habkost TYPE_RISCV_VIRT_MACHINE) 34cdfc19e4SAlistair Francis 35*e6faee65SAnup Patel typedef enum RISCVVirtAIAType { 36*e6faee65SAnup Patel VIRT_AIA_TYPE_NONE = 0, 37*e6faee65SAnup Patel VIRT_AIA_TYPE_APLIC, 38*e6faee65SAnup Patel } RISCVVirtAIAType; 39*e6faee65SAnup Patel 40db1015e9SEduardo Habkost struct RISCVVirtState { 4104331d0bSMichael Clark /*< private >*/ 42cdfc19e4SAlistair Francis MachineState parent; 4304331d0bSMichael Clark 4404331d0bSMichael Clark /*< public >*/ 4518df0b46SAnup Patel RISCVHartArrayState soc[VIRT_SOCKETS_MAX]; 46*e6faee65SAnup Patel DeviceState *irqchip[VIRT_SOCKETS_MAX]; 4771eb522cSAlistair Francis PFlashCFI01 *flash[2]; 480489348dSAsherah Connor FWCfgState *fw_cfg; 49cdfc19e4SAlistair Francis 5004331d0bSMichael Clark int fdt_size; 51954886eaSAnup Patel bool have_aclint; 52*e6faee65SAnup Patel RISCVVirtAIAType aia_type; 53db1015e9SEduardo Habkost }; 5404331d0bSMichael Clark 5504331d0bSMichael Clark enum { 5604331d0bSMichael Clark VIRT_DEBUG, 5704331d0bSMichael Clark VIRT_MROM, 5804331d0bSMichael Clark VIRT_TEST, 5967b5ef30SAnup Patel VIRT_RTC, 6004331d0bSMichael Clark VIRT_CLINT, 61954886eaSAnup Patel VIRT_ACLINT_SSWI, 6204331d0bSMichael Clark VIRT_PLIC, 63*e6faee65SAnup Patel VIRT_APLIC_M, 64*e6faee65SAnup Patel VIRT_APLIC_S, 6504331d0bSMichael Clark VIRT_UART0, 6604331d0bSMichael Clark VIRT_VIRTIO, 670489348dSAsherah Connor VIRT_FW_CFG, 6871eb522cSAlistair Francis VIRT_FLASH, 696d56e396SAlistair Francis VIRT_DRAM, 706d56e396SAlistair Francis VIRT_PCIE_MMIO, 716d56e396SAlistair Francis VIRT_PCIE_PIO, 726d56e396SAlistair Francis VIRT_PCIE_ECAM 7304331d0bSMichael Clark }; 7404331d0bSMichael Clark 7504331d0bSMichael Clark enum { 7604331d0bSMichael Clark UART0_IRQ = 10, 7767b5ef30SAnup Patel RTC_IRQ = 11, 7804331d0bSMichael Clark VIRTIO_IRQ = 1, /* 1 to 8 */ 7904331d0bSMichael Clark VIRTIO_COUNT = 8, 806d56e396SAlistair Francis PCIE_IRQ = 0x20, /* 32 to 35 */ 8163b695f2SAlistair Francis VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */ 8204331d0bSMichael Clark }; 8304331d0bSMichael Clark 84*e6faee65SAnup Patel #define VIRT_IRQCHIP_NUM_SOURCES 127 85*e6faee65SAnup Patel #define VIRT_IRQCHIP_NUM_PRIO_BITS 3 86*e6faee65SAnup Patel 870feb4a71SAlistair Francis #define VIRT_PLIC_PRIORITY_BASE 0x04 8804331d0bSMichael Clark #define VIRT_PLIC_PENDING_BASE 0x1000 8904331d0bSMichael Clark #define VIRT_PLIC_ENABLE_BASE 0x2000 9004331d0bSMichael Clark #define VIRT_PLIC_ENABLE_STRIDE 0x80 9104331d0bSMichael Clark #define VIRT_PLIC_CONTEXT_BASE 0x200000 9204331d0bSMichael Clark #define VIRT_PLIC_CONTEXT_STRIDE 0x1000 9318df0b46SAnup Patel #define VIRT_PLIC_SIZE(__num_context) \ 9418df0b46SAnup Patel (VIRT_PLIC_CONTEXT_BASE + (__num_context) * VIRT_PLIC_CONTEXT_STRIDE) 9504331d0bSMichael Clark 966d56e396SAlistair Francis #define FDT_PCI_ADDR_CELLS 3 976d56e396SAlistair Francis #define FDT_PCI_INT_CELLS 1 986d56e396SAlistair Francis #define FDT_PLIC_INT_CELLS 1 99*e6faee65SAnup Patel #define FDT_APLIC_INT_CELLS 2 100*e6faee65SAnup Patel #define FDT_MAX_INT_CELLS 2 101*e6faee65SAnup Patel #define FDT_MAX_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ 102*e6faee65SAnup Patel 1 + FDT_MAX_INT_CELLS) 103*e6faee65SAnup Patel #define FDT_PLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ 104*e6faee65SAnup Patel 1 + FDT_PLIC_INT_CELLS) 105*e6faee65SAnup Patel #define FDT_APLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ 106*e6faee65SAnup Patel 1 + FDT_APLIC_INT_CELLS) 1076d56e396SAlistair Francis 10804331d0bSMichael Clark #endif 109