104331d0bSMichael Clark /* 25b558380SMichael Clark * QEMU RISC-V VirtIO machine interface 304331d0bSMichael Clark * 404331d0bSMichael Clark * Copyright (c) 2017 SiFive, Inc. 504331d0bSMichael Clark * 604331d0bSMichael Clark * This program is free software; you can redistribute it and/or modify it 704331d0bSMichael Clark * under the terms and conditions of the GNU General Public License, 804331d0bSMichael Clark * version 2 or later, as published by the Free Software Foundation. 904331d0bSMichael Clark * 1004331d0bSMichael Clark * This program is distributed in the hope it will be useful, but WITHOUT 1104331d0bSMichael Clark * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1204331d0bSMichael Clark * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1304331d0bSMichael Clark * more details. 1404331d0bSMichael Clark * 1504331d0bSMichael Clark * You should have received a copy of the GNU General Public License along with 1604331d0bSMichael Clark * this program. If not, see <http://www.gnu.org/licenses/>. 1704331d0bSMichael Clark */ 1804331d0bSMichael Clark 194996b128SMichael Clark #ifndef HW_RISCV_VIRT_H 204996b128SMichael Clark #define HW_RISCV_VIRT_H 2104331d0bSMichael Clark 22*ec150c7eSMarkus Armbruster #include "hw/riscv/riscv_hart.h" 23*ec150c7eSMarkus Armbruster #include "hw/sysbus.h" 24*ec150c7eSMarkus Armbruster 2504331d0bSMichael Clark typedef struct { 2604331d0bSMichael Clark /*< private >*/ 2704331d0bSMichael Clark SysBusDevice parent_obj; 2804331d0bSMichael Clark 2904331d0bSMichael Clark /*< public >*/ 3004331d0bSMichael Clark RISCVHartArrayState soc; 3104331d0bSMichael Clark DeviceState *plic; 3204331d0bSMichael Clark void *fdt; 3304331d0bSMichael Clark int fdt_size; 3404331d0bSMichael Clark } RISCVVirtState; 3504331d0bSMichael Clark 3604331d0bSMichael Clark enum { 3704331d0bSMichael Clark VIRT_DEBUG, 3804331d0bSMichael Clark VIRT_MROM, 3904331d0bSMichael Clark VIRT_TEST, 4004331d0bSMichael Clark VIRT_CLINT, 4104331d0bSMichael Clark VIRT_PLIC, 4204331d0bSMichael Clark VIRT_UART0, 4304331d0bSMichael Clark VIRT_VIRTIO, 446d56e396SAlistair Francis VIRT_DRAM, 456d56e396SAlistair Francis VIRT_PCIE_MMIO, 466d56e396SAlistair Francis VIRT_PCIE_PIO, 476d56e396SAlistair Francis VIRT_PCIE_ECAM 4804331d0bSMichael Clark }; 4904331d0bSMichael Clark 5004331d0bSMichael Clark enum { 5104331d0bSMichael Clark UART0_IRQ = 10, 5204331d0bSMichael Clark VIRTIO_IRQ = 1, /* 1 to 8 */ 5304331d0bSMichael Clark VIRTIO_COUNT = 8, 546d56e396SAlistair Francis PCIE_IRQ = 0x20, /* 32 to 35 */ 5563b695f2SAlistair Francis VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */ 5604331d0bSMichael Clark }; 5704331d0bSMichael Clark 582a8756edSMichael Clark enum { 592a8756edSMichael Clark VIRT_CLOCK_FREQ = 1000000000 602a8756edSMichael Clark }; 612a8756edSMichael Clark 6204331d0bSMichael Clark #define VIRT_PLIC_HART_CONFIG "MS" 6304331d0bSMichael Clark #define VIRT_PLIC_NUM_SOURCES 127 6404331d0bSMichael Clark #define VIRT_PLIC_NUM_PRIORITIES 7 650feb4a71SAlistair Francis #define VIRT_PLIC_PRIORITY_BASE 0x04 6604331d0bSMichael Clark #define VIRT_PLIC_PENDING_BASE 0x1000 6704331d0bSMichael Clark #define VIRT_PLIC_ENABLE_BASE 0x2000 6804331d0bSMichael Clark #define VIRT_PLIC_ENABLE_STRIDE 0x80 6904331d0bSMichael Clark #define VIRT_PLIC_CONTEXT_BASE 0x200000 7004331d0bSMichael Clark #define VIRT_PLIC_CONTEXT_STRIDE 0x1000 7104331d0bSMichael Clark 726d56e396SAlistair Francis #define FDT_PCI_ADDR_CELLS 3 736d56e396SAlistair Francis #define FDT_PCI_INT_CELLS 1 746d56e396SAlistair Francis #define FDT_PLIC_ADDR_CELLS 0 756d56e396SAlistair Francis #define FDT_PLIC_INT_CELLS 1 766d56e396SAlistair Francis #define FDT_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + 1 + \ 776d56e396SAlistair Francis FDT_PLIC_ADDR_CELLS + FDT_PLIC_INT_CELLS) 786d56e396SAlistair Francis 7904331d0bSMichael Clark #if defined(TARGET_RISCV32) 808903bf6eSAlistair Francis #define VIRT_CPU TYPE_RISCV_CPU_BASE32 8104331d0bSMichael Clark #elif defined(TARGET_RISCV64) 828903bf6eSAlistair Francis #define VIRT_CPU TYPE_RISCV_CPU_BASE64 8304331d0bSMichael Clark #endif 8404331d0bSMichael Clark 8504331d0bSMichael Clark #endif 86