1 #include "qemu/osdep.h" 2 #include "qemu-common.h" 3 #include "cpu.h" 4 #include "hw/hw.h" 5 #include "hw/boards.h" 6 #include "qemu/error-report.h" 7 #include "sysemu/kvm.h" 8 #include "kvm_arm.h" 9 #include "internals.h" 10 #include "migration/cpu.h" 11 12 static bool vfp_needed(void *opaque) 13 { 14 ARMCPU *cpu = opaque; 15 CPUARMState *env = &cpu->env; 16 17 return arm_feature(env, ARM_FEATURE_VFP); 18 } 19 20 static int get_fpscr(QEMUFile *f, void *opaque, size_t size, 21 VMStateField *field) 22 { 23 ARMCPU *cpu = opaque; 24 CPUARMState *env = &cpu->env; 25 uint32_t val = qemu_get_be32(f); 26 27 vfp_set_fpscr(env, val); 28 return 0; 29 } 30 31 static int put_fpscr(QEMUFile *f, void *opaque, size_t size, 32 VMStateField *field, QJSON *vmdesc) 33 { 34 ARMCPU *cpu = opaque; 35 CPUARMState *env = &cpu->env; 36 37 qemu_put_be32(f, vfp_get_fpscr(env)); 38 return 0; 39 } 40 41 static const VMStateInfo vmstate_fpscr = { 42 .name = "fpscr", 43 .get = get_fpscr, 44 .put = put_fpscr, 45 }; 46 47 static const VMStateDescription vmstate_vfp = { 48 .name = "cpu/vfp", 49 .version_id = 3, 50 .minimum_version_id = 3, 51 .needed = vfp_needed, 52 .fields = (VMStateField[]) { 53 VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 64), 54 /* The xregs array is a little awkward because element 1 (FPSCR) 55 * requires a specific accessor, so we have to split it up in 56 * the vmstate: 57 */ 58 VMSTATE_UINT32(env.vfp.xregs[0], ARMCPU), 59 VMSTATE_UINT32_SUB_ARRAY(env.vfp.xregs, ARMCPU, 2, 14), 60 { 61 .name = "fpscr", 62 .version_id = 0, 63 .size = sizeof(uint32_t), 64 .info = &vmstate_fpscr, 65 .flags = VMS_SINGLE, 66 .offset = 0, 67 }, 68 VMSTATE_END_OF_LIST() 69 } 70 }; 71 72 static bool iwmmxt_needed(void *opaque) 73 { 74 ARMCPU *cpu = opaque; 75 CPUARMState *env = &cpu->env; 76 77 return arm_feature(env, ARM_FEATURE_IWMMXT); 78 } 79 80 static const VMStateDescription vmstate_iwmmxt = { 81 .name = "cpu/iwmmxt", 82 .version_id = 1, 83 .minimum_version_id = 1, 84 .needed = iwmmxt_needed, 85 .fields = (VMStateField[]) { 86 VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16), 87 VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16), 88 VMSTATE_END_OF_LIST() 89 } 90 }; 91 92 static bool m_needed(void *opaque) 93 { 94 ARMCPU *cpu = opaque; 95 CPUARMState *env = &cpu->env; 96 97 return arm_feature(env, ARM_FEATURE_M); 98 } 99 100 static const VMStateDescription vmstate_m = { 101 .name = "cpu/m", 102 .version_id = 4, 103 .minimum_version_id = 4, 104 .needed = m_needed, 105 .fields = (VMStateField[]) { 106 VMSTATE_UINT32(env.v7m.vecbase, ARMCPU), 107 VMSTATE_UINT32(env.v7m.basepri, ARMCPU), 108 VMSTATE_UINT32(env.v7m.control, ARMCPU), 109 VMSTATE_UINT32(env.v7m.ccr, ARMCPU), 110 VMSTATE_UINT32(env.v7m.cfsr, ARMCPU), 111 VMSTATE_UINT32(env.v7m.hfsr, ARMCPU), 112 VMSTATE_UINT32(env.v7m.dfsr, ARMCPU), 113 VMSTATE_UINT32(env.v7m.mmfar, ARMCPU), 114 VMSTATE_UINT32(env.v7m.bfar, ARMCPU), 115 VMSTATE_UINT32(env.v7m.mpu_ctrl, ARMCPU), 116 VMSTATE_INT32(env.v7m.exception, ARMCPU), 117 VMSTATE_END_OF_LIST() 118 } 119 }; 120 121 static bool thumb2ee_needed(void *opaque) 122 { 123 ARMCPU *cpu = opaque; 124 CPUARMState *env = &cpu->env; 125 126 return arm_feature(env, ARM_FEATURE_THUMB2EE); 127 } 128 129 static const VMStateDescription vmstate_thumb2ee = { 130 .name = "cpu/thumb2ee", 131 .version_id = 1, 132 .minimum_version_id = 1, 133 .needed = thumb2ee_needed, 134 .fields = (VMStateField[]) { 135 VMSTATE_UINT32(env.teecr, ARMCPU), 136 VMSTATE_UINT32(env.teehbr, ARMCPU), 137 VMSTATE_END_OF_LIST() 138 } 139 }; 140 141 static bool pmsav7_needed(void *opaque) 142 { 143 ARMCPU *cpu = opaque; 144 CPUARMState *env = &cpu->env; 145 146 return arm_feature(env, ARM_FEATURE_PMSA) && 147 arm_feature(env, ARM_FEATURE_V7); 148 } 149 150 static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id) 151 { 152 ARMCPU *cpu = opaque; 153 154 return cpu->env.cp15.c6_rgnr < cpu->pmsav7_dregion; 155 } 156 157 static const VMStateDescription vmstate_pmsav7 = { 158 .name = "cpu/pmsav7", 159 .version_id = 1, 160 .minimum_version_id = 1, 161 .needed = pmsav7_needed, 162 .fields = (VMStateField[]) { 163 VMSTATE_VARRAY_UINT32(env.pmsav7.drbar, ARMCPU, pmsav7_dregion, 0, 164 vmstate_info_uint32, uint32_t), 165 VMSTATE_VARRAY_UINT32(env.pmsav7.drsr, ARMCPU, pmsav7_dregion, 0, 166 vmstate_info_uint32, uint32_t), 167 VMSTATE_VARRAY_UINT32(env.pmsav7.dracr, ARMCPU, pmsav7_dregion, 0, 168 vmstate_info_uint32, uint32_t), 169 VMSTATE_VALIDATE("rgnr is valid", pmsav7_rgnr_vmstate_validate), 170 VMSTATE_END_OF_LIST() 171 } 172 }; 173 174 static int get_cpsr(QEMUFile *f, void *opaque, size_t size, 175 VMStateField *field) 176 { 177 ARMCPU *cpu = opaque; 178 CPUARMState *env = &cpu->env; 179 uint32_t val = qemu_get_be32(f); 180 181 env->aarch64 = ((val & PSTATE_nRW) == 0); 182 183 if (is_a64(env)) { 184 pstate_write(env, val); 185 return 0; 186 } 187 188 cpsr_write(env, val, 0xffffffff, CPSRWriteRaw); 189 return 0; 190 } 191 192 static int put_cpsr(QEMUFile *f, void *opaque, size_t size, 193 VMStateField *field, QJSON *vmdesc) 194 { 195 ARMCPU *cpu = opaque; 196 CPUARMState *env = &cpu->env; 197 uint32_t val; 198 199 if (is_a64(env)) { 200 val = pstate_read(env); 201 } else { 202 val = cpsr_read(env); 203 } 204 205 qemu_put_be32(f, val); 206 return 0; 207 } 208 209 static const VMStateInfo vmstate_cpsr = { 210 .name = "cpsr", 211 .get = get_cpsr, 212 .put = put_cpsr, 213 }; 214 215 static int get_power(QEMUFile *f, void *opaque, size_t size, 216 VMStateField *field) 217 { 218 ARMCPU *cpu = opaque; 219 bool powered_off = qemu_get_byte(f); 220 cpu->power_state = powered_off ? PSCI_OFF : PSCI_ON; 221 return 0; 222 } 223 224 static int put_power(QEMUFile *f, void *opaque, size_t size, 225 VMStateField *field, QJSON *vmdesc) 226 { 227 ARMCPU *cpu = opaque; 228 229 /* Migration should never happen while we transition power states */ 230 231 if (cpu->power_state == PSCI_ON || 232 cpu->power_state == PSCI_OFF) { 233 bool powered_off = (cpu->power_state == PSCI_OFF) ? true : false; 234 qemu_put_byte(f, powered_off); 235 return 0; 236 } else { 237 return 1; 238 } 239 } 240 241 static const VMStateInfo vmstate_powered_off = { 242 .name = "powered_off", 243 .get = get_power, 244 .put = put_power, 245 }; 246 247 static void cpu_pre_save(void *opaque) 248 { 249 ARMCPU *cpu = opaque; 250 251 if (kvm_enabled()) { 252 if (!write_kvmstate_to_list(cpu)) { 253 /* This should never fail */ 254 abort(); 255 } 256 } else { 257 if (!write_cpustate_to_list(cpu)) { 258 /* This should never fail. */ 259 abort(); 260 } 261 } 262 263 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; 264 memcpy(cpu->cpreg_vmstate_indexes, cpu->cpreg_indexes, 265 cpu->cpreg_array_len * sizeof(uint64_t)); 266 memcpy(cpu->cpreg_vmstate_values, cpu->cpreg_values, 267 cpu->cpreg_array_len * sizeof(uint64_t)); 268 } 269 270 static int cpu_post_load(void *opaque, int version_id) 271 { 272 ARMCPU *cpu = opaque; 273 int i, v; 274 275 /* Update the values list from the incoming migration data. 276 * Anything in the incoming data which we don't know about is 277 * a migration failure; anything we know about but the incoming 278 * data doesn't specify retains its current (reset) value. 279 * The indexes list remains untouched -- we only inspect the 280 * incoming migration index list so we can match the values array 281 * entries with the right slots in our own values array. 282 */ 283 284 for (i = 0, v = 0; i < cpu->cpreg_array_len 285 && v < cpu->cpreg_vmstate_array_len; i++) { 286 if (cpu->cpreg_vmstate_indexes[v] > cpu->cpreg_indexes[i]) { 287 /* register in our list but not incoming : skip it */ 288 continue; 289 } 290 if (cpu->cpreg_vmstate_indexes[v] < cpu->cpreg_indexes[i]) { 291 /* register in their list but not ours: fail migration */ 292 return -1; 293 } 294 /* matching register, copy the value over */ 295 cpu->cpreg_values[i] = cpu->cpreg_vmstate_values[v]; 296 v++; 297 } 298 299 if (kvm_enabled()) { 300 if (!write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE)) { 301 return -1; 302 } 303 /* Note that it's OK for the TCG side not to know about 304 * every register in the list; KVM is authoritative if 305 * we're using it. 306 */ 307 write_list_to_cpustate(cpu); 308 } else { 309 if (!write_list_to_cpustate(cpu)) { 310 return -1; 311 } 312 } 313 314 hw_breakpoint_update_all(cpu); 315 hw_watchpoint_update_all(cpu); 316 317 return 0; 318 } 319 320 const VMStateDescription vmstate_arm_cpu = { 321 .name = "cpu", 322 .version_id = 22, 323 .minimum_version_id = 22, 324 .pre_save = cpu_pre_save, 325 .post_load = cpu_post_load, 326 .fields = (VMStateField[]) { 327 VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16), 328 VMSTATE_UINT64_ARRAY(env.xregs, ARMCPU, 32), 329 VMSTATE_UINT64(env.pc, ARMCPU), 330 { 331 .name = "cpsr", 332 .version_id = 0, 333 .size = sizeof(uint32_t), 334 .info = &vmstate_cpsr, 335 .flags = VMS_SINGLE, 336 .offset = 0, 337 }, 338 VMSTATE_UINT32(env.spsr, ARMCPU), 339 VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8), 340 VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 8), 341 VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 8), 342 VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5), 343 VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5), 344 VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4), 345 VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 4), 346 /* The length-check must come before the arrays to avoid 347 * incoming data possibly overflowing the array. 348 */ 349 VMSTATE_INT32_POSITIVE_LE(cpreg_vmstate_array_len, ARMCPU), 350 VMSTATE_VARRAY_INT32(cpreg_vmstate_indexes, ARMCPU, 351 cpreg_vmstate_array_len, 352 0, vmstate_info_uint64, uint64_t), 353 VMSTATE_VARRAY_INT32(cpreg_vmstate_values, ARMCPU, 354 cpreg_vmstate_array_len, 355 0, vmstate_info_uint64, uint64_t), 356 VMSTATE_UINT64(env.exclusive_addr, ARMCPU), 357 VMSTATE_UINT64(env.exclusive_val, ARMCPU), 358 VMSTATE_UINT64(env.exclusive_high, ARMCPU), 359 VMSTATE_UINT64(env.features, ARMCPU), 360 VMSTATE_UINT32(env.exception.syndrome, ARMCPU), 361 VMSTATE_UINT32(env.exception.fsr, ARMCPU), 362 VMSTATE_UINT64(env.exception.vaddress, ARMCPU), 363 VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU), 364 VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU), 365 { 366 .name = "power_state", 367 .version_id = 0, 368 .size = sizeof(bool), 369 .info = &vmstate_powered_off, 370 .flags = VMS_SINGLE, 371 .offset = 0, 372 }, 373 VMSTATE_END_OF_LIST() 374 }, 375 .subsections = (const VMStateDescription*[]) { 376 &vmstate_vfp, 377 &vmstate_iwmmxt, 378 &vmstate_m, 379 &vmstate_thumb2ee, 380 &vmstate_pmsav7, 381 NULL 382 } 383 }; 384