xref: /qemu/target/i386/svm.h (revision 24b34590)
1fcf5ef2aSThomas Huth #ifndef SVM_H
2fcf5ef2aSThomas Huth #define SVM_H
3fcf5ef2aSThomas Huth 
4fcf5ef2aSThomas Huth #define TLB_CONTROL_DO_NOTHING 0
5fcf5ef2aSThomas Huth #define TLB_CONTROL_FLUSH_ALL_ASID 1
6fcf5ef2aSThomas Huth 
7fcf5ef2aSThomas Huth #define V_TPR_MASK 0x0f
8fcf5ef2aSThomas Huth 
9fcf5ef2aSThomas Huth #define V_IRQ_SHIFT 8
10fcf5ef2aSThomas Huth #define V_IRQ_MASK (1 << V_IRQ_SHIFT)
11fcf5ef2aSThomas Huth 
12900eeca5SLara Lazier #define V_GIF_ENABLED_SHIFT 25
13900eeca5SLara Lazier #define V_GIF_ENABLED_MASK (1 << V_GIF_ENABLED_SHIFT)
14900eeca5SLara Lazier 
15900eeca5SLara Lazier #define V_GIF_SHIFT 9
16900eeca5SLara Lazier #define V_GIF_MASK (1 << V_GIF_SHIFT)
17900eeca5SLara Lazier 
18fcf5ef2aSThomas Huth #define V_INTR_PRIO_SHIFT 16
19fcf5ef2aSThomas Huth #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
20fcf5ef2aSThomas Huth 
21fcf5ef2aSThomas Huth #define V_IGN_TPR_SHIFT 20
22fcf5ef2aSThomas Huth #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
23fcf5ef2aSThomas Huth 
24fcf5ef2aSThomas Huth #define V_INTR_MASKING_SHIFT 24
25fcf5ef2aSThomas Huth #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
26fcf5ef2aSThomas Huth 
2752fb8ad3SLara Lazier #define V_VMLOAD_VMSAVE_ENABLED_MASK (1 << 1)
2852fb8ad3SLara Lazier 
29fcf5ef2aSThomas Huth #define SVM_INTERRUPT_SHADOW_MASK 1
30fcf5ef2aSThomas Huth 
31fcf5ef2aSThomas Huth #define SVM_IOIO_STR_SHIFT 2
32fcf5ef2aSThomas Huth #define SVM_IOIO_REP_SHIFT 3
33fcf5ef2aSThomas Huth #define SVM_IOIO_SIZE_SHIFT 4
34fcf5ef2aSThomas Huth #define SVM_IOIO_ASIZE_SHIFT 7
35fcf5ef2aSThomas Huth 
36fcf5ef2aSThomas Huth #define SVM_IOIO_TYPE_MASK 1
37fcf5ef2aSThomas Huth #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
38fcf5ef2aSThomas Huth #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
39fcf5ef2aSThomas Huth #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
40fcf5ef2aSThomas Huth #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
41fcf5ef2aSThomas Huth 
42fcf5ef2aSThomas Huth #define SVM_EVTINJ_VEC_MASK 0xff
43fcf5ef2aSThomas Huth 
44fcf5ef2aSThomas Huth #define SVM_EVTINJ_TYPE_SHIFT 8
45fcf5ef2aSThomas Huth #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
46fcf5ef2aSThomas Huth 
47fcf5ef2aSThomas Huth #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
48fcf5ef2aSThomas Huth #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
49fcf5ef2aSThomas Huth #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
50fcf5ef2aSThomas Huth #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
51fcf5ef2aSThomas Huth 
52fcf5ef2aSThomas Huth #define SVM_EVTINJ_VALID (1 << 31)
53fcf5ef2aSThomas Huth #define SVM_EVTINJ_VALID_ERR (1 << 11)
54fcf5ef2aSThomas Huth 
55fcf5ef2aSThomas Huth #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
56fcf5ef2aSThomas Huth 
57fcf5ef2aSThomas Huth #define	SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
58fcf5ef2aSThomas Huth #define	SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
59fcf5ef2aSThomas Huth #define	SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
60fcf5ef2aSThomas Huth #define	SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
61fcf5ef2aSThomas Huth 
62fcf5ef2aSThomas Huth #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
63fcf5ef2aSThomas Huth #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
64fcf5ef2aSThomas Huth 
65fcf5ef2aSThomas Huth #define	SVM_EXIT_READ_CR0 	0x000
66fcf5ef2aSThomas Huth #define	SVM_EXIT_READ_CR3 	0x003
67fcf5ef2aSThomas Huth #define	SVM_EXIT_READ_CR4 	0x004
68fcf5ef2aSThomas Huth #define	SVM_EXIT_READ_CR8 	0x008
69fcf5ef2aSThomas Huth #define	SVM_EXIT_WRITE_CR0 	0x010
70fcf5ef2aSThomas Huth #define	SVM_EXIT_WRITE_CR3 	0x013
71fcf5ef2aSThomas Huth #define	SVM_EXIT_WRITE_CR4 	0x014
72fcf5ef2aSThomas Huth #define	SVM_EXIT_WRITE_CR8 	0x018
73fcf5ef2aSThomas Huth #define	SVM_EXIT_READ_DR0 	0x020
74fcf5ef2aSThomas Huth #define	SVM_EXIT_READ_DR1 	0x021
75fcf5ef2aSThomas Huth #define	SVM_EXIT_READ_DR2 	0x022
76fcf5ef2aSThomas Huth #define	SVM_EXIT_READ_DR3 	0x023
77fcf5ef2aSThomas Huth #define	SVM_EXIT_READ_DR4 	0x024
78fcf5ef2aSThomas Huth #define	SVM_EXIT_READ_DR5 	0x025
79fcf5ef2aSThomas Huth #define	SVM_EXIT_READ_DR6 	0x026
80fcf5ef2aSThomas Huth #define	SVM_EXIT_READ_DR7 	0x027
81fcf5ef2aSThomas Huth #define	SVM_EXIT_WRITE_DR0 	0x030
82fcf5ef2aSThomas Huth #define	SVM_EXIT_WRITE_DR1 	0x031
83fcf5ef2aSThomas Huth #define	SVM_EXIT_WRITE_DR2 	0x032
84fcf5ef2aSThomas Huth #define	SVM_EXIT_WRITE_DR3 	0x033
85fcf5ef2aSThomas Huth #define	SVM_EXIT_WRITE_DR4 	0x034
86fcf5ef2aSThomas Huth #define	SVM_EXIT_WRITE_DR5 	0x035
87fcf5ef2aSThomas Huth #define	SVM_EXIT_WRITE_DR6 	0x036
88fcf5ef2aSThomas Huth #define	SVM_EXIT_WRITE_DR7 	0x037
89fcf5ef2aSThomas Huth #define SVM_EXIT_EXCP_BASE      0x040
90fcf5ef2aSThomas Huth #define SVM_EXIT_INTR		0x060
91fcf5ef2aSThomas Huth #define SVM_EXIT_NMI		0x061
92fcf5ef2aSThomas Huth #define SVM_EXIT_SMI		0x062
93fcf5ef2aSThomas Huth #define SVM_EXIT_INIT		0x063
94fcf5ef2aSThomas Huth #define SVM_EXIT_VINTR		0x064
95fcf5ef2aSThomas Huth #define SVM_EXIT_CR0_SEL_WRITE	0x065
96fcf5ef2aSThomas Huth #define SVM_EXIT_IDTR_READ	0x066
97fcf5ef2aSThomas Huth #define SVM_EXIT_GDTR_READ	0x067
98fcf5ef2aSThomas Huth #define SVM_EXIT_LDTR_READ	0x068
99fcf5ef2aSThomas Huth #define SVM_EXIT_TR_READ	0x069
100fcf5ef2aSThomas Huth #define SVM_EXIT_IDTR_WRITE	0x06a
101fcf5ef2aSThomas Huth #define SVM_EXIT_GDTR_WRITE	0x06b
102fcf5ef2aSThomas Huth #define SVM_EXIT_LDTR_WRITE	0x06c
103fcf5ef2aSThomas Huth #define SVM_EXIT_TR_WRITE	0x06d
104fcf5ef2aSThomas Huth #define SVM_EXIT_RDTSC		0x06e
105fcf5ef2aSThomas Huth #define SVM_EXIT_RDPMC		0x06f
106fcf5ef2aSThomas Huth #define SVM_EXIT_PUSHF		0x070
107fcf5ef2aSThomas Huth #define SVM_EXIT_POPF		0x071
108fcf5ef2aSThomas Huth #define SVM_EXIT_CPUID		0x072
109fcf5ef2aSThomas Huth #define SVM_EXIT_RSM		0x073
110fcf5ef2aSThomas Huth #define SVM_EXIT_IRET		0x074
111fcf5ef2aSThomas Huth #define SVM_EXIT_SWINT		0x075
112fcf5ef2aSThomas Huth #define SVM_EXIT_INVD		0x076
113fcf5ef2aSThomas Huth #define SVM_EXIT_PAUSE		0x077
114fcf5ef2aSThomas Huth #define SVM_EXIT_HLT		0x078
115fcf5ef2aSThomas Huth #define SVM_EXIT_INVLPG		0x079
116fcf5ef2aSThomas Huth #define SVM_EXIT_INVLPGA	0x07a
117fcf5ef2aSThomas Huth #define SVM_EXIT_IOIO		0x07b
118fcf5ef2aSThomas Huth #define SVM_EXIT_MSR		0x07c
119fcf5ef2aSThomas Huth #define SVM_EXIT_TASK_SWITCH	0x07d
120fcf5ef2aSThomas Huth #define SVM_EXIT_FERR_FREEZE	0x07e
121fcf5ef2aSThomas Huth #define SVM_EXIT_SHUTDOWN	0x07f
122fcf5ef2aSThomas Huth #define SVM_EXIT_VMRUN		0x080
123fcf5ef2aSThomas Huth #define SVM_EXIT_VMMCALL	0x081
124fcf5ef2aSThomas Huth #define SVM_EXIT_VMLOAD		0x082
125fcf5ef2aSThomas Huth #define SVM_EXIT_VMSAVE		0x083
126fcf5ef2aSThomas Huth #define SVM_EXIT_STGI		0x084
127fcf5ef2aSThomas Huth #define SVM_EXIT_CLGI		0x085
128fcf5ef2aSThomas Huth #define SVM_EXIT_SKINIT		0x086
129fcf5ef2aSThomas Huth #define SVM_EXIT_RDTSCP		0x087
130fcf5ef2aSThomas Huth #define SVM_EXIT_ICEBP		0x088
131fcf5ef2aSThomas Huth #define SVM_EXIT_WBINVD		0x089
132fcf5ef2aSThomas Huth /* only included in documentation, maybe wrong */
133fcf5ef2aSThomas Huth #define SVM_EXIT_MONITOR	0x08a
134fcf5ef2aSThomas Huth #define SVM_EXIT_MWAIT		0x08b
13524b34590SPaolo Bonzini #define SVM_EXIT_XSETBV		0x08d
136fcf5ef2aSThomas Huth #define SVM_EXIT_NPF  		0x400
137fcf5ef2aSThomas Huth 
138fcf5ef2aSThomas Huth #define SVM_EXIT_ERR		-1
139fcf5ef2aSThomas Huth 
140fcf5ef2aSThomas Huth #define SVM_CR0_SELECTIVE_MASK (1 << 3 | 1) /* TS and MP */
141fcf5ef2aSThomas Huth 
142fe441054SJan Kiszka #define SVM_NPT_ENABLED     (1 << 0)
143fe441054SJan Kiszka 
144fe441054SJan Kiszka #define SVM_NPTEXIT_GPA     (1ULL << 32)
145fe441054SJan Kiszka #define SVM_NPTEXIT_GPT     (1ULL << 33)
146fe441054SJan Kiszka 
147498df2a7SLara Lazier #define SVM_CR0_RESERVED_MASK 0xffffffff00000000U
148498df2a7SLara Lazier 
149481077b2SLara Lazier #define SVM_MSRPM_SIZE		(1ULL << 13)
150481077b2SLara Lazier #define SVM_IOPM_SIZE		((1ULL << 13) + 1)
151481077b2SLara Lazier 
152fcf5ef2aSThomas Huth struct QEMU_PACKED vmcb_control_area {
153fcf5ef2aSThomas Huth 	uint16_t intercept_cr_read;
154fcf5ef2aSThomas Huth 	uint16_t intercept_cr_write;
155fcf5ef2aSThomas Huth 	uint16_t intercept_dr_read;
156fcf5ef2aSThomas Huth 	uint16_t intercept_dr_write;
157fcf5ef2aSThomas Huth 	uint32_t intercept_exceptions;
158fcf5ef2aSThomas Huth 	uint64_t intercept;
159fcf5ef2aSThomas Huth 	uint8_t reserved_1[44];
160fcf5ef2aSThomas Huth 	uint64_t iopm_base_pa;
161fcf5ef2aSThomas Huth 	uint64_t msrpm_base_pa;
162fcf5ef2aSThomas Huth 	uint64_t tsc_offset;
163fcf5ef2aSThomas Huth 	uint32_t asid;
164fcf5ef2aSThomas Huth 	uint8_t tlb_ctl;
165fcf5ef2aSThomas Huth 	uint8_t reserved_2[3];
166fcf5ef2aSThomas Huth 	uint32_t int_ctl;
167fcf5ef2aSThomas Huth 	uint32_t int_vector;
168fcf5ef2aSThomas Huth 	uint32_t int_state;
169fcf5ef2aSThomas Huth 	uint8_t reserved_3[4];
170fcf5ef2aSThomas Huth 	uint64_t exit_code;
171fcf5ef2aSThomas Huth 	uint64_t exit_info_1;
172fcf5ef2aSThomas Huth 	uint64_t exit_info_2;
173fcf5ef2aSThomas Huth 	uint32_t exit_int_info;
174fcf5ef2aSThomas Huth 	uint32_t exit_int_info_err;
175fcf5ef2aSThomas Huth 	uint64_t nested_ctl;
176fcf5ef2aSThomas Huth 	uint8_t reserved_4[16];
177fcf5ef2aSThomas Huth 	uint32_t event_inj;
178fcf5ef2aSThomas Huth 	uint32_t event_inj_err;
179fcf5ef2aSThomas Huth 	uint64_t nested_cr3;
180fcf5ef2aSThomas Huth 	uint64_t lbr_ctl;
181fcf5ef2aSThomas Huth 	uint8_t reserved_5[832];
182fcf5ef2aSThomas Huth };
183fcf5ef2aSThomas Huth 
184fcf5ef2aSThomas Huth struct QEMU_PACKED vmcb_seg {
185fcf5ef2aSThomas Huth 	uint16_t selector;
186fcf5ef2aSThomas Huth 	uint16_t attrib;
187fcf5ef2aSThomas Huth 	uint32_t limit;
188fcf5ef2aSThomas Huth 	uint64_t base;
189fcf5ef2aSThomas Huth };
190fcf5ef2aSThomas Huth 
191fcf5ef2aSThomas Huth struct QEMU_PACKED vmcb_save_area {
192fcf5ef2aSThomas Huth 	struct vmcb_seg es;
193fcf5ef2aSThomas Huth 	struct vmcb_seg cs;
194fcf5ef2aSThomas Huth 	struct vmcb_seg ss;
195fcf5ef2aSThomas Huth 	struct vmcb_seg ds;
196fcf5ef2aSThomas Huth 	struct vmcb_seg fs;
197fcf5ef2aSThomas Huth 	struct vmcb_seg gs;
198fcf5ef2aSThomas Huth 	struct vmcb_seg gdtr;
199fcf5ef2aSThomas Huth 	struct vmcb_seg ldtr;
200fcf5ef2aSThomas Huth 	struct vmcb_seg idtr;
201fcf5ef2aSThomas Huth 	struct vmcb_seg tr;
202fcf5ef2aSThomas Huth 	uint8_t reserved_1[43];
203fcf5ef2aSThomas Huth 	uint8_t cpl;
204fcf5ef2aSThomas Huth 	uint8_t reserved_2[4];
205fcf5ef2aSThomas Huth 	uint64_t efer;
206fcf5ef2aSThomas Huth 	uint8_t reserved_3[112];
207fcf5ef2aSThomas Huth 	uint64_t cr4;
208fcf5ef2aSThomas Huth 	uint64_t cr3;
209fcf5ef2aSThomas Huth 	uint64_t cr0;
210fcf5ef2aSThomas Huth 	uint64_t dr7;
211fcf5ef2aSThomas Huth 	uint64_t dr6;
212fcf5ef2aSThomas Huth 	uint64_t rflags;
213fcf5ef2aSThomas Huth 	uint64_t rip;
214fcf5ef2aSThomas Huth 	uint8_t reserved_4[88];
215fcf5ef2aSThomas Huth 	uint64_t rsp;
216fcf5ef2aSThomas Huth 	uint8_t reserved_5[24];
217fcf5ef2aSThomas Huth 	uint64_t rax;
218fcf5ef2aSThomas Huth 	uint64_t star;
219fcf5ef2aSThomas Huth 	uint64_t lstar;
220fcf5ef2aSThomas Huth 	uint64_t cstar;
221fcf5ef2aSThomas Huth 	uint64_t sfmask;
222fcf5ef2aSThomas Huth 	uint64_t kernel_gs_base;
223fcf5ef2aSThomas Huth 	uint64_t sysenter_cs;
224fcf5ef2aSThomas Huth 	uint64_t sysenter_esp;
225fcf5ef2aSThomas Huth 	uint64_t sysenter_eip;
226fcf5ef2aSThomas Huth 	uint64_t cr2;
227fcf5ef2aSThomas Huth 	uint8_t reserved_6[32];
228fcf5ef2aSThomas Huth 	uint64_t g_pat;
229fcf5ef2aSThomas Huth 	uint64_t dbgctl;
230fcf5ef2aSThomas Huth 	uint64_t br_from;
231fcf5ef2aSThomas Huth 	uint64_t br_to;
232fcf5ef2aSThomas Huth 	uint64_t last_excp_from;
233fcf5ef2aSThomas Huth 	uint64_t last_excp_to;
234fcf5ef2aSThomas Huth };
235fcf5ef2aSThomas Huth 
236fcf5ef2aSThomas Huth struct QEMU_PACKED vmcb {
237fcf5ef2aSThomas Huth 	struct vmcb_control_area control;
238fcf5ef2aSThomas Huth 	struct vmcb_save_area save;
239fcf5ef2aSThomas Huth };
240fcf5ef2aSThomas Huth 
241fcf5ef2aSThomas Huth #endif
242