xref: /qemu/target/riscv/meson.build (revision 138ca49a) 
1# FIXME extra_args should accept files()
2dir = meson.current_source_dir()
3gen32 = [
4  decodetree.process('insn16.decode', extra_args: [dir / 'insn16-32.decode', '--static-decode=decode_insn16', '--insnwidth=16']),
5  decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
6]
7
8gen64 = [
9  decodetree.process('insn16.decode', extra_args: [dir / 'insn16-64.decode', '--static-decode=decode_insn16', '--insnwidth=16']),
10  decodetree.process('insn32.decode', extra_args: [dir / 'insn32-64.decode', '--static-decode=decode_insn32']),
11]
12
13riscv_ss = ss.source_set()
14riscv_ss.add(when: 'TARGET_RISCV32', if_true: gen32)
15riscv_ss.add(when: 'TARGET_RISCV64', if_true: gen64)
16riscv_ss.add(files(
17  'cpu.c',
18  'cpu_helper.c',
19  'csr.c',
20  'fpu_helper.c',
21  'gdbstub.c',
22  'op_helper.c',
23  'vector_helper.c',
24  'translate.c',
25))
26
27riscv_softmmu_ss = ss.source_set()
28riscv_softmmu_ss.add(files(
29  'pmp.c',
30  'monitor.c',
31  'machine.c'
32))
33
34target_arch += {'riscv': riscv_ss}
35target_softmmu_arch += {'riscv': riscv_softmmu_ss}
36