1 /* 2 * SH4 emulation 3 * 4 * Copyright (c) 2005 Samuel Tardieu 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "qemu/osdep.h" 20 21 #include "cpu.h" 22 #include "exec/exec-all.h" 23 #include "exec/log.h" 24 25 #if !defined(CONFIG_USER_ONLY) 26 #include "hw/sh4/sh_intc.h" 27 #endif 28 29 #if defined(CONFIG_USER_ONLY) 30 31 void superh_cpu_do_interrupt(CPUState *cs) 32 { 33 cs->exception_index = -1; 34 } 35 36 int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, 37 int mmu_idx) 38 { 39 SuperHCPU *cpu = SUPERH_CPU(cs); 40 CPUSH4State *env = &cpu->env; 41 42 env->tea = address; 43 cs->exception_index = -1; 44 switch (rw) { 45 case 0: 46 cs->exception_index = 0x0a0; 47 break; 48 case 1: 49 cs->exception_index = 0x0c0; 50 break; 51 case 2: 52 cs->exception_index = 0x0a0; 53 break; 54 } 55 return 1; 56 } 57 58 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr) 59 { 60 /* For user mode, only U0 area is cacheable. */ 61 return !(addr & 0x80000000); 62 } 63 64 #else /* !CONFIG_USER_ONLY */ 65 66 #define MMU_OK 0 67 #define MMU_ITLB_MISS (-1) 68 #define MMU_ITLB_MULTIPLE (-2) 69 #define MMU_ITLB_VIOLATION (-3) 70 #define MMU_DTLB_MISS_READ (-4) 71 #define MMU_DTLB_MISS_WRITE (-5) 72 #define MMU_DTLB_INITIAL_WRITE (-6) 73 #define MMU_DTLB_VIOLATION_READ (-7) 74 #define MMU_DTLB_VIOLATION_WRITE (-8) 75 #define MMU_DTLB_MULTIPLE (-9) 76 #define MMU_DTLB_MISS (-10) 77 #define MMU_IADDR_ERROR (-11) 78 #define MMU_DADDR_ERROR_READ (-12) 79 #define MMU_DADDR_ERROR_WRITE (-13) 80 81 void superh_cpu_do_interrupt(CPUState *cs) 82 { 83 SuperHCPU *cpu = SUPERH_CPU(cs); 84 CPUSH4State *env = &cpu->env; 85 int do_irq = cs->interrupt_request & CPU_INTERRUPT_HARD; 86 int do_exp, irq_vector = cs->exception_index; 87 88 /* prioritize exceptions over interrupts */ 89 90 do_exp = cs->exception_index != -1; 91 do_irq = do_irq && (cs->exception_index == -1); 92 93 if (env->sr & (1u << SR_BL)) { 94 if (do_exp && cs->exception_index != 0x1e0) { 95 cs->exception_index = 0x000; /* masked exception -> reset */ 96 } 97 if (do_irq && !env->in_sleep) { 98 return; /* masked */ 99 } 100 } 101 env->in_sleep = 0; 102 103 if (do_irq) { 104 irq_vector = sh_intc_get_pending_vector(env->intc_handle, 105 (env->sr >> 4) & 0xf); 106 if (irq_vector == -1) { 107 return; /* masked */ 108 } 109 } 110 111 if (qemu_loglevel_mask(CPU_LOG_INT)) { 112 const char *expname; 113 switch (cs->exception_index) { 114 case 0x0e0: 115 expname = "addr_error"; 116 break; 117 case 0x040: 118 expname = "tlb_miss"; 119 break; 120 case 0x0a0: 121 expname = "tlb_violation"; 122 break; 123 case 0x180: 124 expname = "illegal_instruction"; 125 break; 126 case 0x1a0: 127 expname = "slot_illegal_instruction"; 128 break; 129 case 0x800: 130 expname = "fpu_disable"; 131 break; 132 case 0x820: 133 expname = "slot_fpu"; 134 break; 135 case 0x100: 136 expname = "data_write"; 137 break; 138 case 0x060: 139 expname = "dtlb_miss_write"; 140 break; 141 case 0x0c0: 142 expname = "dtlb_violation_write"; 143 break; 144 case 0x120: 145 expname = "fpu_exception"; 146 break; 147 case 0x080: 148 expname = "initial_page_write"; 149 break; 150 case 0x160: 151 expname = "trapa"; 152 break; 153 default: 154 expname = do_irq ? "interrupt" : "???"; 155 break; 156 } 157 qemu_log("exception 0x%03x [%s] raised\n", 158 irq_vector, expname); 159 log_cpu_state(cs, 0); 160 } 161 162 env->ssr = cpu_read_sr(env); 163 env->spc = env->pc; 164 env->sgr = env->gregs[15]; 165 env->sr |= (1u << SR_BL) | (1u << SR_MD) | (1u << SR_RB); 166 167 if (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { 168 /* Branch instruction should be executed again before delay slot. */ 169 env->spc -= 2; 170 /* Clear flags for exception/interrupt routine. */ 171 env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); 172 } 173 174 if (do_exp) { 175 env->expevt = cs->exception_index; 176 switch (cs->exception_index) { 177 case 0x000: 178 case 0x020: 179 case 0x140: 180 env->sr &= ~(1u << SR_FD); 181 env->sr |= 0xf << 4; /* IMASK */ 182 env->pc = 0xa0000000; 183 break; 184 case 0x040: 185 case 0x060: 186 env->pc = env->vbr + 0x400; 187 break; 188 case 0x160: 189 env->spc += 2; /* special case for TRAPA */ 190 /* fall through */ 191 default: 192 env->pc = env->vbr + 0x100; 193 break; 194 } 195 return; 196 } 197 198 if (do_irq) { 199 env->intevt = irq_vector; 200 env->pc = env->vbr + 0x600; 201 return; 202 } 203 } 204 205 static void update_itlb_use(CPUSH4State * env, int itlbnb) 206 { 207 uint8_t or_mask = 0, and_mask = (uint8_t) - 1; 208 209 switch (itlbnb) { 210 case 0: 211 and_mask = 0x1f; 212 break; 213 case 1: 214 and_mask = 0xe7; 215 or_mask = 0x80; 216 break; 217 case 2: 218 and_mask = 0xfb; 219 or_mask = 0x50; 220 break; 221 case 3: 222 or_mask = 0x2c; 223 break; 224 } 225 226 env->mmucr &= (and_mask << 24) | 0x00ffffff; 227 env->mmucr |= (or_mask << 24); 228 } 229 230 static int itlb_replacement(CPUSH4State * env) 231 { 232 SuperHCPU *cpu = sh_env_get_cpu(env); 233 234 if ((env->mmucr & 0xe0000000) == 0xe0000000) { 235 return 0; 236 } 237 if ((env->mmucr & 0x98000000) == 0x18000000) { 238 return 1; 239 } 240 if ((env->mmucr & 0x54000000) == 0x04000000) { 241 return 2; 242 } 243 if ((env->mmucr & 0x2c000000) == 0x00000000) { 244 return 3; 245 } 246 cpu_abort(CPU(cpu), "Unhandled itlb_replacement"); 247 } 248 249 /* Find the corresponding entry in the right TLB 250 Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE 251 */ 252 static int find_tlb_entry(CPUSH4State * env, target_ulong address, 253 tlb_t * entries, uint8_t nbtlb, int use_asid) 254 { 255 int match = MMU_DTLB_MISS; 256 uint32_t start, end; 257 uint8_t asid; 258 int i; 259 260 asid = env->pteh & 0xff; 261 262 for (i = 0; i < nbtlb; i++) { 263 if (!entries[i].v) 264 continue; /* Invalid entry */ 265 if (!entries[i].sh && use_asid && entries[i].asid != asid) 266 continue; /* Bad ASID */ 267 start = (entries[i].vpn << 10) & ~(entries[i].size - 1); 268 end = start + entries[i].size - 1; 269 if (address >= start && address <= end) { /* Match */ 270 if (match != MMU_DTLB_MISS) 271 return MMU_DTLB_MULTIPLE; /* Multiple match */ 272 match = i; 273 } 274 } 275 return match; 276 } 277 278 static void increment_urc(CPUSH4State * env) 279 { 280 uint8_t urb, urc; 281 282 /* Increment URC */ 283 urb = ((env->mmucr) >> 18) & 0x3f; 284 urc = ((env->mmucr) >> 10) & 0x3f; 285 urc++; 286 if ((urb > 0 && urc > urb) || urc > (UTLB_SIZE - 1)) 287 urc = 0; 288 env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10); 289 } 290 291 /* Copy and utlb entry into itlb 292 Return entry 293 */ 294 static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb) 295 { 296 int itlb; 297 298 tlb_t * ientry; 299 itlb = itlb_replacement(env); 300 ientry = &env->itlb[itlb]; 301 if (ientry->v) { 302 tlb_flush_page(CPU(sh_env_get_cpu(env)), ientry->vpn << 10); 303 } 304 *ientry = env->utlb[utlb]; 305 update_itlb_use(env, itlb); 306 return itlb; 307 } 308 309 /* Find itlb entry 310 Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE 311 */ 312 static int find_itlb_entry(CPUSH4State * env, target_ulong address, 313 int use_asid) 314 { 315 int e; 316 317 e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid); 318 if (e == MMU_DTLB_MULTIPLE) { 319 e = MMU_ITLB_MULTIPLE; 320 } else if (e == MMU_DTLB_MISS) { 321 e = MMU_ITLB_MISS; 322 } else if (e >= 0) { 323 update_itlb_use(env, e); 324 } 325 return e; 326 } 327 328 /* Find utlb entry 329 Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */ 330 static int find_utlb_entry(CPUSH4State * env, target_ulong address, int use_asid) 331 { 332 /* per utlb access */ 333 increment_urc(env); 334 335 /* Return entry */ 336 return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid); 337 } 338 339 /* Match address against MMU 340 Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE, 341 MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ, 342 MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS, 343 MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION, 344 MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE. 345 */ 346 static int get_mmu_address(CPUSH4State * env, target_ulong * physical, 347 int *prot, target_ulong address, 348 int rw, int access_type) 349 { 350 int use_asid, n; 351 tlb_t *matching = NULL; 352 353 use_asid = !(env->mmucr & MMUCR_SV) || !(env->sr & (1u << SR_MD)); 354 355 if (rw == 2) { 356 n = find_itlb_entry(env, address, use_asid); 357 if (n >= 0) { 358 matching = &env->itlb[n]; 359 if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) { 360 n = MMU_ITLB_VIOLATION; 361 } else { 362 *prot = PAGE_EXEC; 363 } 364 } else { 365 n = find_utlb_entry(env, address, use_asid); 366 if (n >= 0) { 367 n = copy_utlb_entry_itlb(env, n); 368 matching = &env->itlb[n]; 369 if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) { 370 n = MMU_ITLB_VIOLATION; 371 } else { 372 *prot = PAGE_READ | PAGE_EXEC; 373 if ((matching->pr & 1) && matching->d) { 374 *prot |= PAGE_WRITE; 375 } 376 } 377 } else if (n == MMU_DTLB_MULTIPLE) { 378 n = MMU_ITLB_MULTIPLE; 379 } else if (n == MMU_DTLB_MISS) { 380 n = MMU_ITLB_MISS; 381 } 382 } 383 } else { 384 n = find_utlb_entry(env, address, use_asid); 385 if (n >= 0) { 386 matching = &env->utlb[n]; 387 if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) { 388 n = (rw == 1) ? MMU_DTLB_VIOLATION_WRITE : 389 MMU_DTLB_VIOLATION_READ; 390 } else if ((rw == 1) && !(matching->pr & 1)) { 391 n = MMU_DTLB_VIOLATION_WRITE; 392 } else if ((rw == 1) && !matching->d) { 393 n = MMU_DTLB_INITIAL_WRITE; 394 } else { 395 *prot = PAGE_READ; 396 if ((matching->pr & 1) && matching->d) { 397 *prot |= PAGE_WRITE; 398 } 399 } 400 } else if (n == MMU_DTLB_MISS) { 401 n = (rw == 1) ? MMU_DTLB_MISS_WRITE : 402 MMU_DTLB_MISS_READ; 403 } 404 } 405 if (n >= 0) { 406 n = MMU_OK; 407 *physical = ((matching->ppn << 10) & ~(matching->size - 1)) | 408 (address & (matching->size - 1)); 409 } 410 return n; 411 } 412 413 static int get_physical_address(CPUSH4State * env, target_ulong * physical, 414 int *prot, target_ulong address, 415 int rw, int access_type) 416 { 417 /* P1, P2 and P4 areas do not use translation */ 418 if ((address >= 0x80000000 && address < 0xc0000000) || 419 address >= 0xe0000000) { 420 if (!(env->sr & (1u << SR_MD)) 421 && (address < 0xe0000000 || address >= 0xe4000000)) { 422 /* Unauthorized access in user mode (only store queues are available) */ 423 fprintf(stderr, "Unauthorized access\n"); 424 if (rw == 0) 425 return MMU_DADDR_ERROR_READ; 426 else if (rw == 1) 427 return MMU_DADDR_ERROR_WRITE; 428 else 429 return MMU_IADDR_ERROR; 430 } 431 if (address >= 0x80000000 && address < 0xc0000000) { 432 /* Mask upper 3 bits for P1 and P2 areas */ 433 *physical = address & 0x1fffffff; 434 } else { 435 *physical = address; 436 } 437 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 438 return MMU_OK; 439 } 440 441 /* If MMU is disabled, return the corresponding physical page */ 442 if (!(env->mmucr & MMUCR_AT)) { 443 *physical = address & 0x1FFFFFFF; 444 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 445 return MMU_OK; 446 } 447 448 /* We need to resort to the MMU */ 449 return get_mmu_address(env, physical, prot, address, rw, access_type); 450 } 451 452 int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, 453 int mmu_idx) 454 { 455 SuperHCPU *cpu = SUPERH_CPU(cs); 456 CPUSH4State *env = &cpu->env; 457 target_ulong physical; 458 int prot, ret, access_type; 459 460 access_type = ACCESS_INT; 461 ret = 462 get_physical_address(env, &physical, &prot, address, rw, 463 access_type); 464 465 if (ret != MMU_OK) { 466 env->tea = address; 467 if (ret != MMU_DTLB_MULTIPLE && ret != MMU_ITLB_MULTIPLE) { 468 env->pteh = (env->pteh & PTEH_ASID_MASK) | 469 (address & PTEH_VPN_MASK); 470 } 471 switch (ret) { 472 case MMU_ITLB_MISS: 473 case MMU_DTLB_MISS_READ: 474 cs->exception_index = 0x040; 475 break; 476 case MMU_DTLB_MULTIPLE: 477 case MMU_ITLB_MULTIPLE: 478 cs->exception_index = 0x140; 479 break; 480 case MMU_ITLB_VIOLATION: 481 cs->exception_index = 0x0a0; 482 break; 483 case MMU_DTLB_MISS_WRITE: 484 cs->exception_index = 0x060; 485 break; 486 case MMU_DTLB_INITIAL_WRITE: 487 cs->exception_index = 0x080; 488 break; 489 case MMU_DTLB_VIOLATION_READ: 490 cs->exception_index = 0x0a0; 491 break; 492 case MMU_DTLB_VIOLATION_WRITE: 493 cs->exception_index = 0x0c0; 494 break; 495 case MMU_IADDR_ERROR: 496 case MMU_DADDR_ERROR_READ: 497 cs->exception_index = 0x0e0; 498 break; 499 case MMU_DADDR_ERROR_WRITE: 500 cs->exception_index = 0x100; 501 break; 502 default: 503 cpu_abort(cs, "Unhandled MMU fault"); 504 } 505 return 1; 506 } 507 508 address &= TARGET_PAGE_MASK; 509 physical &= TARGET_PAGE_MASK; 510 511 tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE); 512 return 0; 513 } 514 515 hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 516 { 517 SuperHCPU *cpu = SUPERH_CPU(cs); 518 target_ulong physical; 519 int prot; 520 521 get_physical_address(&cpu->env, &physical, &prot, addr, 0, 0); 522 return physical; 523 } 524 525 void cpu_load_tlb(CPUSH4State * env) 526 { 527 SuperHCPU *cpu = sh_env_get_cpu(env); 528 int n = cpu_mmucr_urc(env->mmucr); 529 tlb_t * entry = &env->utlb[n]; 530 531 if (entry->v) { 532 /* Overwriting valid entry in utlb. */ 533 target_ulong address = entry->vpn << 10; 534 tlb_flush_page(CPU(cpu), address); 535 } 536 537 /* Take values into cpu status from registers. */ 538 entry->asid = (uint8_t)cpu_pteh_asid(env->pteh); 539 entry->vpn = cpu_pteh_vpn(env->pteh); 540 entry->v = (uint8_t)cpu_ptel_v(env->ptel); 541 entry->ppn = cpu_ptel_ppn(env->ptel); 542 entry->sz = (uint8_t)cpu_ptel_sz(env->ptel); 543 switch (entry->sz) { 544 case 0: /* 00 */ 545 entry->size = 1024; /* 1K */ 546 break; 547 case 1: /* 01 */ 548 entry->size = 1024 * 4; /* 4K */ 549 break; 550 case 2: /* 10 */ 551 entry->size = 1024 * 64; /* 64K */ 552 break; 553 case 3: /* 11 */ 554 entry->size = 1024 * 1024; /* 1M */ 555 break; 556 default: 557 cpu_abort(CPU(cpu), "Unhandled load_tlb"); 558 break; 559 } 560 entry->sh = (uint8_t)cpu_ptel_sh(env->ptel); 561 entry->c = (uint8_t)cpu_ptel_c(env->ptel); 562 entry->pr = (uint8_t)cpu_ptel_pr(env->ptel); 563 entry->d = (uint8_t)cpu_ptel_d(env->ptel); 564 entry->wt = (uint8_t)cpu_ptel_wt(env->ptel); 565 entry->sa = (uint8_t)cpu_ptea_sa(env->ptea); 566 entry->tc = (uint8_t)cpu_ptea_tc(env->ptea); 567 } 568 569 void cpu_sh4_invalidate_tlb(CPUSH4State *s) 570 { 571 int i; 572 573 /* UTLB */ 574 for (i = 0; i < UTLB_SIZE; i++) { 575 tlb_t * entry = &s->utlb[i]; 576 entry->v = 0; 577 } 578 /* ITLB */ 579 for (i = 0; i < ITLB_SIZE; i++) { 580 tlb_t * entry = &s->itlb[i]; 581 entry->v = 0; 582 } 583 584 tlb_flush(CPU(sh_env_get_cpu(s))); 585 } 586 587 uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s, 588 hwaddr addr) 589 { 590 int index = (addr & 0x00000300) >> 8; 591 tlb_t * entry = &s->itlb[index]; 592 593 return (entry->vpn << 10) | 594 (entry->v << 8) | 595 (entry->asid); 596 } 597 598 void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr, 599 uint32_t mem_value) 600 { 601 uint32_t vpn = (mem_value & 0xfffffc00) >> 10; 602 uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8); 603 uint8_t asid = (uint8_t)(mem_value & 0x000000ff); 604 605 int index = (addr & 0x00000300) >> 8; 606 tlb_t * entry = &s->itlb[index]; 607 if (entry->v) { 608 /* Overwriting valid entry in itlb. */ 609 target_ulong address = entry->vpn << 10; 610 tlb_flush_page(CPU(sh_env_get_cpu(s)), address); 611 } 612 entry->asid = asid; 613 entry->vpn = vpn; 614 entry->v = v; 615 } 616 617 uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s, 618 hwaddr addr) 619 { 620 int array = (addr & 0x00800000) >> 23; 621 int index = (addr & 0x00000300) >> 8; 622 tlb_t * entry = &s->itlb[index]; 623 624 if (array == 0) { 625 /* ITLB Data Array 1 */ 626 return (entry->ppn << 10) | 627 (entry->v << 8) | 628 (entry->pr << 5) | 629 ((entry->sz & 1) << 6) | 630 ((entry->sz & 2) << 4) | 631 (entry->c << 3) | 632 (entry->sh << 1); 633 } else { 634 /* ITLB Data Array 2 */ 635 return (entry->tc << 1) | 636 (entry->sa); 637 } 638 } 639 640 void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr, 641 uint32_t mem_value) 642 { 643 int array = (addr & 0x00800000) >> 23; 644 int index = (addr & 0x00000300) >> 8; 645 tlb_t * entry = &s->itlb[index]; 646 647 if (array == 0) { 648 /* ITLB Data Array 1 */ 649 if (entry->v) { 650 /* Overwriting valid entry in utlb. */ 651 target_ulong address = entry->vpn << 10; 652 tlb_flush_page(CPU(sh_env_get_cpu(s)), address); 653 } 654 entry->ppn = (mem_value & 0x1ffffc00) >> 10; 655 entry->v = (mem_value & 0x00000100) >> 8; 656 entry->sz = (mem_value & 0x00000080) >> 6 | 657 (mem_value & 0x00000010) >> 4; 658 entry->pr = (mem_value & 0x00000040) >> 5; 659 entry->c = (mem_value & 0x00000008) >> 3; 660 entry->sh = (mem_value & 0x00000002) >> 1; 661 } else { 662 /* ITLB Data Array 2 */ 663 entry->tc = (mem_value & 0x00000008) >> 3; 664 entry->sa = (mem_value & 0x00000007); 665 } 666 } 667 668 uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s, 669 hwaddr addr) 670 { 671 int index = (addr & 0x00003f00) >> 8; 672 tlb_t * entry = &s->utlb[index]; 673 674 increment_urc(s); /* per utlb access */ 675 676 return (entry->vpn << 10) | 677 (entry->v << 8) | 678 (entry->asid); 679 } 680 681 void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr, 682 uint32_t mem_value) 683 { 684 int associate = addr & 0x0000080; 685 uint32_t vpn = (mem_value & 0xfffffc00) >> 10; 686 uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9); 687 uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8); 688 uint8_t asid = (uint8_t)(mem_value & 0x000000ff); 689 int use_asid = !(s->mmucr & MMUCR_SV) || !(s->sr & (1u << SR_MD)); 690 691 if (associate) { 692 int i; 693 tlb_t * utlb_match_entry = NULL; 694 int needs_tlb_flush = 0; 695 696 /* search UTLB */ 697 for (i = 0; i < UTLB_SIZE; i++) { 698 tlb_t * entry = &s->utlb[i]; 699 if (!entry->v) 700 continue; 701 702 if (entry->vpn == vpn 703 && (!use_asid || entry->asid == asid || entry->sh)) { 704 if (utlb_match_entry) { 705 CPUState *cs = CPU(sh_env_get_cpu(s)); 706 707 /* Multiple TLB Exception */ 708 cs->exception_index = 0x140; 709 s->tea = addr; 710 break; 711 } 712 if (entry->v && !v) 713 needs_tlb_flush = 1; 714 entry->v = v; 715 entry->d = d; 716 utlb_match_entry = entry; 717 } 718 increment_urc(s); /* per utlb access */ 719 } 720 721 /* search ITLB */ 722 for (i = 0; i < ITLB_SIZE; i++) { 723 tlb_t * entry = &s->itlb[i]; 724 if (entry->vpn == vpn 725 && (!use_asid || entry->asid == asid || entry->sh)) { 726 if (entry->v && !v) 727 needs_tlb_flush = 1; 728 if (utlb_match_entry) 729 *entry = *utlb_match_entry; 730 else 731 entry->v = v; 732 break; 733 } 734 } 735 736 if (needs_tlb_flush) { 737 tlb_flush_page(CPU(sh_env_get_cpu(s)), vpn << 10); 738 } 739 740 } else { 741 int index = (addr & 0x00003f00) >> 8; 742 tlb_t * entry = &s->utlb[index]; 743 if (entry->v) { 744 CPUState *cs = CPU(sh_env_get_cpu(s)); 745 746 /* Overwriting valid entry in utlb. */ 747 target_ulong address = entry->vpn << 10; 748 tlb_flush_page(cs, address); 749 } 750 entry->asid = asid; 751 entry->vpn = vpn; 752 entry->d = d; 753 entry->v = v; 754 increment_urc(s); 755 } 756 } 757 758 uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s, 759 hwaddr addr) 760 { 761 int array = (addr & 0x00800000) >> 23; 762 int index = (addr & 0x00003f00) >> 8; 763 tlb_t * entry = &s->utlb[index]; 764 765 increment_urc(s); /* per utlb access */ 766 767 if (array == 0) { 768 /* ITLB Data Array 1 */ 769 return (entry->ppn << 10) | 770 (entry->v << 8) | 771 (entry->pr << 5) | 772 ((entry->sz & 1) << 6) | 773 ((entry->sz & 2) << 4) | 774 (entry->c << 3) | 775 (entry->d << 2) | 776 (entry->sh << 1) | 777 (entry->wt); 778 } else { 779 /* ITLB Data Array 2 */ 780 return (entry->tc << 1) | 781 (entry->sa); 782 } 783 } 784 785 void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr, 786 uint32_t mem_value) 787 { 788 int array = (addr & 0x00800000) >> 23; 789 int index = (addr & 0x00003f00) >> 8; 790 tlb_t * entry = &s->utlb[index]; 791 792 increment_urc(s); /* per utlb access */ 793 794 if (array == 0) { 795 /* UTLB Data Array 1 */ 796 if (entry->v) { 797 /* Overwriting valid entry in utlb. */ 798 target_ulong address = entry->vpn << 10; 799 tlb_flush_page(CPU(sh_env_get_cpu(s)), address); 800 } 801 entry->ppn = (mem_value & 0x1ffffc00) >> 10; 802 entry->v = (mem_value & 0x00000100) >> 8; 803 entry->sz = (mem_value & 0x00000080) >> 6 | 804 (mem_value & 0x00000010) >> 4; 805 entry->pr = (mem_value & 0x00000060) >> 5; 806 entry->c = (mem_value & 0x00000008) >> 3; 807 entry->d = (mem_value & 0x00000004) >> 2; 808 entry->sh = (mem_value & 0x00000002) >> 1; 809 entry->wt = (mem_value & 0x00000001); 810 } else { 811 /* UTLB Data Array 2 */ 812 entry->tc = (mem_value & 0x00000008) >> 3; 813 entry->sa = (mem_value & 0x00000007); 814 } 815 } 816 817 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr) 818 { 819 int n; 820 int use_asid = !(env->mmucr & MMUCR_SV) || !(env->sr & (1u << SR_MD)); 821 822 /* check area */ 823 if (env->sr & (1u << SR_MD)) { 824 /* For privileged mode, P2 and P4 area is not cacheable. */ 825 if ((0xA0000000 <= addr && addr < 0xC0000000) || 0xE0000000 <= addr) 826 return 0; 827 } else { 828 /* For user mode, only U0 area is cacheable. */ 829 if (0x80000000 <= addr) 830 return 0; 831 } 832 833 /* 834 * TODO : Evaluate CCR and check if the cache is on or off. 835 * Now CCR is not in CPUSH4State, but in SH7750State. 836 * When you move the ccr into CPUSH4State, the code will be 837 * as follows. 838 */ 839 #if 0 840 /* check if operand cache is enabled or not. */ 841 if (!(env->ccr & 1)) 842 return 0; 843 #endif 844 845 /* if MMU is off, no check for TLB. */ 846 if (env->mmucr & MMUCR_AT) 847 return 1; 848 849 /* check TLB */ 850 n = find_tlb_entry(env, addr, env->itlb, ITLB_SIZE, use_asid); 851 if (n >= 0) 852 return env->itlb[n].c; 853 854 n = find_tlb_entry(env, addr, env->utlb, UTLB_SIZE, use_asid); 855 if (n >= 0) 856 return env->utlb[n].c; 857 858 return 0; 859 } 860 861 #endif 862 863 bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 864 { 865 if (interrupt_request & CPU_INTERRUPT_HARD) { 866 superh_cpu_do_interrupt(cs); 867 return true; 868 } 869 return false; 870 } 871