1 /* 2 * FPU op helpers 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "exec/exec-all.h" 23 #include "exec/helper-proto.h" 24 #include "fpu/softfloat.h" 25 26 #define QT0 (env->qt0) 27 #define QT1 (env->qt1) 28 29 static inline float128 f128_in(Int128 i) 30 { 31 union { 32 Int128 i; 33 float128 f; 34 } u; 35 36 u.i = i; 37 return u.f; 38 } 39 40 static inline Int128 f128_ret(float128 f) 41 { 42 union { 43 Int128 i; 44 float128 f; 45 } u; 46 47 u.f = f; 48 return u.i; 49 } 50 51 static target_ulong do_check_ieee_exceptions(CPUSPARCState *env, uintptr_t ra) 52 { 53 target_ulong status = get_float_exception_flags(&env->fp_status); 54 target_ulong fsr = env->fsr; 55 56 if (unlikely(status)) { 57 /* Keep exception flags clear for next time. */ 58 set_float_exception_flags(0, &env->fp_status); 59 60 /* Copy IEEE 754 flags into FSR */ 61 if (status & float_flag_invalid) { 62 fsr |= FSR_NVC; 63 } 64 if (status & float_flag_overflow) { 65 fsr |= FSR_OFC; 66 } 67 if (status & float_flag_underflow) { 68 fsr |= FSR_UFC; 69 } 70 if (status & float_flag_divbyzero) { 71 fsr |= FSR_DZC; 72 } 73 if (status & float_flag_inexact) { 74 fsr |= FSR_NXC; 75 } 76 77 if ((fsr & FSR_CEXC_MASK) & ((fsr & FSR_TEM_MASK) >> 23)) { 78 CPUState *cs = env_cpu(env); 79 80 /* Unmasked exception, generate a trap. Note that while 81 the helper is marked as NO_WG, we can get away with 82 writing to cpu state along the exception path, since 83 TCG generated code will never see the write. */ 84 env->fsr = fsr | FSR_FTT_IEEE_EXCP; 85 cs->exception_index = TT_FP_EXCP; 86 cpu_loop_exit_restore(cs, ra); 87 } else { 88 /* Accumulate exceptions */ 89 fsr |= (fsr & FSR_CEXC_MASK) << 5; 90 } 91 } 92 93 return fsr; 94 } 95 96 target_ulong helper_check_ieee_exceptions(CPUSPARCState *env) 97 { 98 return do_check_ieee_exceptions(env, GETPC()); 99 } 100 101 #define F_BINOP(name) \ 102 float32 helper_f ## name ## s (CPUSPARCState *env, float32 src1, \ 103 float32 src2) \ 104 { \ 105 return float32_ ## name (src1, src2, &env->fp_status); \ 106 } \ 107 float64 helper_f ## name ## d (CPUSPARCState * env, float64 src1,\ 108 float64 src2) \ 109 { \ 110 return float64_ ## name (src1, src2, &env->fp_status); \ 111 } \ 112 Int128 helper_f ## name ## q(CPUSPARCState * env, Int128 src1, \ 113 Int128 src2) \ 114 { \ 115 return f128_ret(float128_ ## name (f128_in(src1), f128_in(src2), \ 116 &env->fp_status)); \ 117 } 118 119 F_BINOP(add); 120 F_BINOP(sub); 121 F_BINOP(mul); 122 F_BINOP(div); 123 #undef F_BINOP 124 125 float64 helper_fsmuld(CPUSPARCState *env, float32 src1, float32 src2) 126 { 127 return float64_mul(float32_to_float64(src1, &env->fp_status), 128 float32_to_float64(src2, &env->fp_status), 129 &env->fp_status); 130 } 131 132 void helper_fdmulq(CPUSPARCState *env, float64 src1, float64 src2) 133 { 134 QT0 = float128_mul(float64_to_float128(src1, &env->fp_status), 135 float64_to_float128(src2, &env->fp_status), 136 &env->fp_status); 137 } 138 139 /* Integer to float conversion. */ 140 float32 helper_fitos(CPUSPARCState *env, int32_t src) 141 { 142 return int32_to_float32(src, &env->fp_status); 143 } 144 145 float64 helper_fitod(CPUSPARCState *env, int32_t src) 146 { 147 return int32_to_float64(src, &env->fp_status); 148 } 149 150 void helper_fitoq(CPUSPARCState *env, int32_t src) 151 { 152 QT0 = int32_to_float128(src, &env->fp_status); 153 } 154 155 #ifdef TARGET_SPARC64 156 float32 helper_fxtos(CPUSPARCState *env, int64_t src) 157 { 158 return int64_to_float32(src, &env->fp_status); 159 } 160 161 float64 helper_fxtod(CPUSPARCState *env, int64_t src) 162 { 163 return int64_to_float64(src, &env->fp_status); 164 } 165 166 void helper_fxtoq(CPUSPARCState *env, int64_t src) 167 { 168 QT0 = int64_to_float128(src, &env->fp_status); 169 } 170 #endif 171 172 /* floating point conversion */ 173 float32 helper_fdtos(CPUSPARCState *env, float64 src) 174 { 175 return float64_to_float32(src, &env->fp_status); 176 } 177 178 float64 helper_fstod(CPUSPARCState *env, float32 src) 179 { 180 return float32_to_float64(src, &env->fp_status); 181 } 182 183 float32 helper_fqtos(CPUSPARCState *env) 184 { 185 return float128_to_float32(QT1, &env->fp_status); 186 } 187 188 void helper_fstoq(CPUSPARCState *env, float32 src) 189 { 190 QT0 = float32_to_float128(src, &env->fp_status); 191 } 192 193 float64 helper_fqtod(CPUSPARCState *env) 194 { 195 return float128_to_float64(QT1, &env->fp_status); 196 } 197 198 void helper_fdtoq(CPUSPARCState *env, float64 src) 199 { 200 QT0 = float64_to_float128(src, &env->fp_status); 201 } 202 203 /* Float to integer conversion. */ 204 int32_t helper_fstoi(CPUSPARCState *env, float32 src) 205 { 206 return float32_to_int32_round_to_zero(src, &env->fp_status); 207 } 208 209 int32_t helper_fdtoi(CPUSPARCState *env, float64 src) 210 { 211 return float64_to_int32_round_to_zero(src, &env->fp_status); 212 } 213 214 int32_t helper_fqtoi(CPUSPARCState *env) 215 { 216 return float128_to_int32_round_to_zero(QT1, &env->fp_status); 217 } 218 219 #ifdef TARGET_SPARC64 220 int64_t helper_fstox(CPUSPARCState *env, float32 src) 221 { 222 return float32_to_int64_round_to_zero(src, &env->fp_status); 223 } 224 225 int64_t helper_fdtox(CPUSPARCState *env, float64 src) 226 { 227 return float64_to_int64_round_to_zero(src, &env->fp_status); 228 } 229 230 int64_t helper_fqtox(CPUSPARCState *env) 231 { 232 return float128_to_int64_round_to_zero(QT1, &env->fp_status); 233 } 234 #endif 235 236 float32 helper_fsqrts(CPUSPARCState *env, float32 src) 237 { 238 return float32_sqrt(src, &env->fp_status); 239 } 240 241 float64 helper_fsqrtd(CPUSPARCState *env, float64 src) 242 { 243 return float64_sqrt(src, &env->fp_status); 244 } 245 246 Int128 helper_fsqrtq(CPUSPARCState *env, Int128 src) 247 { 248 return f128_ret(float128_sqrt(f128_in(src), &env->fp_status)); 249 } 250 251 #define GEN_FCMP(name, size, reg1, reg2, FS, E) \ 252 target_ulong glue(helper_, name) (CPUSPARCState *env) \ 253 { \ 254 FloatRelation ret; \ 255 target_ulong fsr; \ 256 if (E) { \ 257 ret = glue(size, _compare)(reg1, reg2, &env->fp_status); \ 258 } else { \ 259 ret = glue(size, _compare_quiet)(reg1, reg2, \ 260 &env->fp_status); \ 261 } \ 262 fsr = do_check_ieee_exceptions(env, GETPC()); \ 263 switch (ret) { \ 264 case float_relation_unordered: \ 265 fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \ 266 fsr |= FSR_NVA; \ 267 break; \ 268 case float_relation_less: \ 269 fsr &= ~(FSR_FCC1) << FS; \ 270 fsr |= FSR_FCC0 << FS; \ 271 break; \ 272 case float_relation_greater: \ 273 fsr &= ~(FSR_FCC0) << FS; \ 274 fsr |= FSR_FCC1 << FS; \ 275 break; \ 276 default: \ 277 fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ 278 break; \ 279 } \ 280 return fsr; \ 281 } 282 #define GEN_FCMP_T(name, size, FS, E) \ 283 target_ulong glue(helper_, name)(CPUSPARCState *env, size src1, size src2)\ 284 { \ 285 FloatRelation ret; \ 286 target_ulong fsr; \ 287 if (E) { \ 288 ret = glue(size, _compare)(src1, src2, &env->fp_status); \ 289 } else { \ 290 ret = glue(size, _compare_quiet)(src1, src2, \ 291 &env->fp_status); \ 292 } \ 293 fsr = do_check_ieee_exceptions(env, GETPC()); \ 294 switch (ret) { \ 295 case float_relation_unordered: \ 296 fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \ 297 break; \ 298 case float_relation_less: \ 299 fsr &= ~(FSR_FCC1 << FS); \ 300 fsr |= FSR_FCC0 << FS; \ 301 break; \ 302 case float_relation_greater: \ 303 fsr &= ~(FSR_FCC0 << FS); \ 304 fsr |= FSR_FCC1 << FS; \ 305 break; \ 306 default: \ 307 fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ 308 break; \ 309 } \ 310 return fsr; \ 311 } 312 313 GEN_FCMP_T(fcmps, float32, 0, 0); 314 GEN_FCMP_T(fcmpd, float64, 0, 0); 315 316 GEN_FCMP_T(fcmpes, float32, 0, 1); 317 GEN_FCMP_T(fcmped, float64, 0, 1); 318 319 GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0); 320 GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1); 321 322 #ifdef TARGET_SPARC64 323 GEN_FCMP_T(fcmps_fcc1, float32, 22, 0); 324 GEN_FCMP_T(fcmpd_fcc1, float64, 22, 0); 325 GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0); 326 327 GEN_FCMP_T(fcmps_fcc2, float32, 24, 0); 328 GEN_FCMP_T(fcmpd_fcc2, float64, 24, 0); 329 GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0); 330 331 GEN_FCMP_T(fcmps_fcc3, float32, 26, 0); 332 GEN_FCMP_T(fcmpd_fcc3, float64, 26, 0); 333 GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0); 334 335 GEN_FCMP_T(fcmpes_fcc1, float32, 22, 1); 336 GEN_FCMP_T(fcmped_fcc1, float64, 22, 1); 337 GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1); 338 339 GEN_FCMP_T(fcmpes_fcc2, float32, 24, 1); 340 GEN_FCMP_T(fcmped_fcc2, float64, 24, 1); 341 GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1); 342 343 GEN_FCMP_T(fcmpes_fcc3, float32, 26, 1); 344 GEN_FCMP_T(fcmped_fcc3, float64, 26, 1); 345 GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1); 346 #endif 347 #undef GEN_FCMP_T 348 #undef GEN_FCMP 349 350 static void set_fsr(CPUSPARCState *env, target_ulong fsr) 351 { 352 int rnd_mode; 353 354 switch (fsr & FSR_RD_MASK) { 355 case FSR_RD_NEAREST: 356 rnd_mode = float_round_nearest_even; 357 break; 358 default: 359 case FSR_RD_ZERO: 360 rnd_mode = float_round_to_zero; 361 break; 362 case FSR_RD_POS: 363 rnd_mode = float_round_up; 364 break; 365 case FSR_RD_NEG: 366 rnd_mode = float_round_down; 367 break; 368 } 369 set_float_rounding_mode(rnd_mode, &env->fp_status); 370 } 371 372 void helper_set_fsr(CPUSPARCState *env, target_ulong fsr) 373 { 374 set_fsr(env, fsr); 375 } 376