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Revision tags: v8.2.2, v7.2.10, v8.2.1, v8.1.5, v7.2.9, v8.1.4, v7.2.8, v8.2.0, v8.2.0-rc4, v8.2.0-rc3, v8.2.0-rc2, v8.2.0-rc1, v7.2.7, v8.1.3, v8.2.0-rc0 |
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| #
d8c5b92f |
| 03-Nov-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Split fcc out of env->fsr
Represent each fcc field separately from the rest of fsr.
This vastly simplifies floating-point comparisons.
Signed-off-by: Richard Henderson <richard.hender
target/sparc: Split fcc out of env->fsr
Represent each fcc field separately from the rest of fsr.
This vastly simplifies floating-point comparisons.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-22-richard.henderson@linaro.org>
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| #
c9fa8e58 |
| 03-Nov-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Remove cpu_fsr
Drop this field as a tcg global, loading it explicitly in the
few places required. This means that all FPop helpers may
once again be TCG_CALL_NO_WG.
Signed-off-by: Ri
target/sparc: Remove cpu_fsr
Drop this field as a tcg global, loading it explicitly in the
few places required. This means that all FPop helpers may
once again be TCG_CALL_NO_WG.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-21-richard.henderson@linaro.org>
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| #
3590f01e |
| 03-Nov-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Split cexc and ftt from env->fsr
These two fields are adjusted by all FPop insns.
Having them separate makes it easier to set without masking.
Signed-off-by: Richard Henderson <richar
target/sparc: Split cexc and ftt from env->fsr
These two fields are adjusted by all FPop insns.
Having them separate makes it easier to set without masking.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-20-richard.henderson@linaro.org>
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| #
db713911 |
| 03-Nov-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Merge check_ieee_exceptions with FPop helpers
If an exception is to be raised, the destination fp register
should be unmodified. The current implementation is incorrect,
in that doubl
target/sparc: Merge check_ieee_exceptions with FPop helpers
If an exception is to be raised, the destination fp register
should be unmodified. The current implementation is incorrect,
in that double results will be written back before calling
gen_helper_check_ieee_exceptions, despite the placement of
gen_store_fpr_D, since gen_dest_fpr_D returns cpu_fpr[].
We can simplify the entire implementation by having each
FPOp helper call check_ieee_exceptions. For the moment this
requires that all FPop helpers write to the TCG global cpu_fsr,
so remove TCG_CALL_NO_WG from the DEF_HELPER_FLAGS_*.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-19-richard.henderson@linaro.org>
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| #
efeb8b07 |
| 03-Nov-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Clear cexc and ftt in do_check_ieee_exceptions
Don't do the clearing explicitly before each FPop,
rather do it as part of the rest of exception handling.
Signed-off-by: Richard Hender
target/sparc: Clear cexc and ftt in do_check_ieee_exceptions
Don't do the clearing explicitly before each FPop,
rather do it as part of the rest of exception handling.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-18-richard.henderson@linaro.org>
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| #
49bb9725 |
| 03-Nov-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Split ver from env->fsr
This field is read-only. It is easier to store it separately
and merge it only upon read.
While we're at it, use FSR_VER_SHIFT to initialize fpu_version.
Sig
target/sparc: Split ver from env->fsr
This field is read-only. It is easier to store it separately
and merge it only upon read.
While we're at it, use FSR_VER_SHIFT to initialize fpu_version.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-17-richard.henderson@linaro.org>
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| #
1ccd6e13 |
| 03-Nov-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Introduce cpu_get_fsr, cpu_put_fsr
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Mark Cave-Ayland <
target/sparc: Introduce cpu_get_fsr, cpu_put_fsr
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-16-richard.henderson@linaro.org>
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| #
41535ca6 |
| 03-Nov-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Remove qt0, qt1 temporaries
These are no longer used for passing data to/from helpers.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mar
target/sparc: Remove qt0, qt1 temporaries
These are no longer used for passing data to/from helpers.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-15-richard.henderson@linaro.org>
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| #
ba21dc99 |
| 03-Nov-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Use i128 for Fdmulq
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ay
target/sparc: Use i128 for Fdmulq
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-14-richard.henderson@linaro.org>
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| #
fdc50716 |
| 03-Nov-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Use i128 for FdTOq, FxTOq
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.c
target/sparc: Use i128 for FdTOq, FxTOq
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-13-richard.henderson@linaro.org>
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| #
0b2a61cc |
| 03-Nov-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Use i128 for FsTOq, FiTOq
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.c
target/sparc: Use i128 for FsTOq, FiTOq
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-12-richard.henderson@linaro.org>
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| #
f3ceafad |
| 03-Nov-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Use i128 for FCMPq, FCMPEq
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.
target/sparc: Use i128 for FCMPq, FCMPEq
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-11-richard.henderson@linaro.org>
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| #
25a5769e |
| 03-Nov-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Use i128 for FqTOd, FqTOx
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.c
target/sparc: Use i128 for FqTOd, FqTOx
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-10-richard.henderson@linaro.org>
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| #
d81e3efe |
| 03-Nov-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Use i128 for FqTOs, FqTOi
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.c
target/sparc: Use i128 for FqTOs, FqTOi
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-9-richard.henderson@linaro.org>
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| #
16bedf89 |
| 03-Nov-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Use i128 for FADDq, FSUBq, FMULq, FDIVq
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-
target/sparc: Use i128 for FADDq, FSUBq, FMULq, FDIVq
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-8-richard.henderson@linaro.org>
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| #
e41716be |
| 03-Nov-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Use i128 for FSQRTq
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ay
target/sparc: Use i128 for FSQRTq
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-7-richard.henderson@linaro.org>
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| #
daf457d4 |
| 03-Nov-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Inline FNEG, FABS
These are simple bit manipulation insns.
Begin using i128 for float128.
Implement FMOVq with do_qq.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
R
target/sparc: Inline FNEG, FABS
These are simple bit manipulation insns.
Begin using i128 for float128.
Implement FMOVq with do_qq.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-6-richard.henderson@linaro.org>
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Revision tags: v8.1.2 |
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| #
da681406 |
| 05-Oct-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Merge LDFSR, LDXFSR implementations
Combine the helper to a single set_fsr().
Perform the mask and merge inline.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by:
target/sparc: Merge LDFSR, LDXFSR implementations
Combine the helper to a single set_fsr().
Perform the mask and merge inline.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
show more ...
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Revision tags: v8.1.2 |
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| #
da681406 |
| 05-Oct-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Merge LDFSR, LDXFSR implementations
Combine the helper to a single set_fsr().
Perform the mask and merge inline.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by:
target/sparc: Merge LDFSR, LDXFSR implementations
Combine the helper to a single set_fsr().
Perform the mask and merge inline.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
show more ...
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Revision tags: v8.1.2 |
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| #
da681406 |
| 05-Oct-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Merge LDFSR, LDXFSR implementations
Combine the helper to a single set_fsr().
Perform the mask and merge inline.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by:
target/sparc: Merge LDFSR, LDXFSR implementations
Combine the helper to a single set_fsr().
Perform the mask and merge inline.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
show more ...
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Revision tags: v8.1.2 |
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| #
da681406 |
| 05-Oct-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Merge LDFSR, LDXFSR implementations
Combine the helper to a single set_fsr().
Perform the mask and merge inline.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by:
target/sparc: Merge LDFSR, LDXFSR implementations
Combine the helper to a single set_fsr().
Perform the mask and merge inline.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
show more ...
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Revision tags: v8.1.1, v7.2.6, v8.0.5, v8.1.0, v8.1.0-rc4, v8.1.0-rc3, v7.2.5, v8.0.4, v8.1.0-rc2, v8.1.0-rc1, v8.1.0-rc0, v8.0.3, v7.2.4, v8.0.2, v8.0.1, v7.2.3, v7.2.2, v8.0.0, v8.0.0-rc4, v8.0.0-rc3, v7.2.1, v8.0.0-rc2, v8.0.0-rc1, v8.0.0-rc0, v7.2.0, v7.2.0-rc4, v7.2.0-rc3, v7.2.0-rc2, v7.2.0-rc1, v7.2.0-rc0, v7.1.0, v7.1.0-rc4, v7.1.0-rc3, v7.1.0-rc2, v7.1.0-rc1, v7.1.0-rc0, v7.0.0, v7.0.0-rc4, v7.0.0-rc3, v7.0.0-rc2, v7.0.0-rc1, v7.0.0-rc0, v6.1.1, v6.2.0, v6.2.0-rc4, v6.2.0-rc3, v6.2.0-rc2, v6.2.0-rc1, v6.2.0-rc0, v6.0.1, v6.1.0, v6.1.0-rc4, v6.1.0-rc3, v6.1.0-rc2, v6.1.0-rc1, v6.1.0-rc0, v6.0.0, v6.0.0-rc5, v6.0.0-rc4, v6.0.0-rc3, v6.0.0-rc2, v6.0.0-rc1, v6.0.0-rc0, v5.2.0, v5.2.0-rc4, v5.2.0-rc3, v5.2.0-rc2, v5.2.0-rc1, v5.2.0-rc0 |
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| #
5650b549 |
| 23-Oct-2020 |
Chetan Pant <chetan4windows@gmail.com> |
sparc tcg cpus: Fix Lesser GPL version number
There is no "version 2" of the "Lesser" General Public License.
It is either "GPL version 2.0" or "Lesser GPL version 2.1".
This patch replaces all occu
sparc tcg cpus: Fix Lesser GPL version number
There is no "version 2" of the "Lesser" General Public License.
It is either "GPL version 2.0" or "Lesser GPL version 2.1".
This patch replaces all occurrences of "Lesser GPL version 2" with
"Lesser GPL version 2.1" in comment section.
Signed-off-by: Chetan Pant <chetan4windows@gmail.com>
Message-Id: <20201023124235.20130-1-chetan4windows@gmail.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
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Revision tags: v5.0.1, v5.1.0, v5.1.0-rc3, v5.1.0-rc2, v5.1.0-rc1, v5.1.0-rc0, v4.2.1 |
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| #
71bfd65c |
| 05-May-2020 |
Richard Henderson <richard.henderson@linaro.org> |
softfloat: Name compare relation enum
Give the previously unnamed enum a typedef name. Use it in the
prototypes of compare functions. Use it to hold the results
of the compare functions.
Reviewed
softfloat: Name compare relation enum
Give the previously unnamed enum a typedef name. Use it in the
prototypes of compare functions. Use it to hold the results
of the compare functions.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
show more ...
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Revision tags: v5.0.0, v5.0.0-rc4, v5.0.0-rc3, v5.0.0-rc2, v5.0.0-rc1, v5.0.0-rc0, v4.2.0, v4.2.0-rc5, v4.2.0-rc4, v4.2.0-rc3, v4.2.0-rc2, v4.1.1, v4.2.0-rc1, v4.2.0-rc0, v4.0.1, v3.1.1.1, v4.1.0, v4.1.0-rc5, v4.1.0-rc4, v3.1.1, v4.1.0-rc3, v4.1.0-rc2, v4.1.0-rc1, v4.1.0-rc0, v4.0.0, v4.0.0-rc4, v3.0.1, v4.0.0-rc3, v4.0.0-rc2, v4.0.0-rc1 |
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| #
5a59fbce |
| 23-Mar-2019 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Use env_cpu, env_archcpu
Cleanup in the boilerplate that each target must define.
Replace sparc_env_get_cpu with env_archcpu. The combination
CPU(sparc_env_get_cpu) should have used E
target/sparc: Use env_cpu, env_archcpu
Cleanup in the boilerplate that each target must define.
Replace sparc_env_get_cpu with env_archcpu. The combination
CPU(sparc_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
show more ...
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Revision tags: v4.0.0-rc0, v3.1.0, v3.1.0-rc5, v3.1.0-rc4, v3.1.0-rc3, v3.1.0-rc2, v3.1.0-rc1, v3.1.0-rc0, v3.0.0, v3.0.0-rc4, v2.12.1, v3.0.0-rc3, v3.0.0-rc2, v3.0.0-rc1, v3.0.0-rc0, v2.11.2, v2.12.0, v2.12.0-rc4, v2.12.0-rc3, v2.12.0-rc2, v2.12.0-rc1, v2.12.0-rc0, v2.11.1 |
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| #
24f91e81 |
| 19-Jan-2018 |
Alex Bennée <alex.bennee@linaro.org> |
target/*/cpu.h: remove softfloat.h
As cpu.h is another typically widely included file which doesn't need
full access to the softfloat API we can remove the includes from here
as well. Where they do
target/*/cpu.h: remove softfloat.h
As cpu.h is another typically widely included file which doesn't need
full access to the softfloat API we can remove the includes from here
as well. Where they do need types it's typically for float_status and
the rounding modes so we move that to softfloat-types.h as well.
As a result of not having softfloat in every cpu.h call we now need to
add it to various helpers that do need the full softfloat.h
definitions.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[For PPC parts]
Acked-by: David Gibson <david@gibson.dropbear.id.au>
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