4a20ac40 | 21-Feb-2024 |
Tianlan Zhou <bobby825@126.com> |
docs/system: Update description for input grab key
Input grab key should be Ctrl-Alt-g, not just Ctrl-Alt.
Fixes: f8d2c9369b ("sdl: use ctrl-alt-g as grab hotkey") Signed-off-by: Tianlan Zhou <bobb
docs/system: Update description for input grab key
Input grab key should be Ctrl-Alt-g, not just Ctrl-Alt.
Fixes: f8d2c9369b ("sdl: use ctrl-alt-g as grab hotkey") Signed-off-by: Tianlan Zhou <bobby825@126.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
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c555b504 | 20-Feb-2024 |
Manos Pitsidianakis <manos.pitsidianakis@linaro.org> |
docs: correct typos
Correct typos automatically found with the `typos` tool <https://crates.io/crates/typos>
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Alex Be
docs: correct typos
Correct typos automatically found with the `typos` tool <https://crates.io/crates/typos>
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> (mjt: trivial fixup) Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
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f780e63f | 06-Feb-2024 |
Peter Maydell <peter.maydell@linaro.org> |
docs: Add documentation for the mps3-an536 board
Add documentation for the mps3-an536 board type.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd
docs: Add documentation for the mps3-an536 board
Add documentation for the mps3-an536 board type.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240206132931.38376-14-peter.maydell@linaro.org
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8700ee15 | 26-Jan-2024 |
Jonathan Cameron <Jonathan.Cameron@huawei.com> |
hw/cxl: Standardize all references on CXL r3.1 and minor updates
Previously not all references mentioned any spec version at all. Given r3.1 is the current specification available for evaluation at
hw/cxl: Standardize all references on CXL r3.1 and minor updates
Previously not all references mentioned any spec version at all. Given r3.1 is the current specification available for evaluation at www.computeexpresslink.org update references to refer to that. Hopefully this won't become a never ending job.
A few structure definitions have been updated to add new fields. Defaults of 0 and read only are valid choices for these new DVSEC registers so go with that for now.
There are additional error codes and some of the 'questions' in the comments are resolved now.
Update documentation reference to point to the CXL r3.1 specification with naming closer to what is on the cover.
For cases where there are structure version numbers, add defines so they can be found next to the register definitions.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20240126121636.24611-6-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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887d5775 | 04-Jan-2024 |
Leo Yan <leo.yan@linaro.org> |
docs/system: Add vhost-user-input documentation
This adds basic documentation for vhost-user-input.
Signed-off-by: Leo Yan <leo.yan@linaro.org> Message-Id: <20231120043721.50555-3-leo.yan@linaro.or
docs/system: Add vhost-user-input documentation
This adds basic documentation for vhost-user-input.
Signed-off-by: Leo Yan <leo.yan@linaro.org> Message-Id: <20231120043721.50555-3-leo.yan@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240104210945.1223134-10-alex.bennee@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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e7fe9122 | 04-Jan-2024 |
Alex Bennée <alex.bennee@linaro.org> |
docs/system: add a basic enumeration of vhost-user devices
Make it clear the vhost-user-device is intended for expert use only.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <2024
docs/system: add a basic enumeration of vhost-user devices
Make it clear the vhost-user-device is intended for expert use only.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240104210945.1223134-8-alex.bennee@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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30c917b0 | 10-May-2023 |
Daniel P. Berrangé <berrange@redhat.com> |
docs: re-generate x86_64 ABI compatibility CSV
This picks up the new EPYC-Genoa, SapphireRapids & GraniteRapids CPUs, removes the now deleted Icelake-Client CPU, and adds the newer versions of many
docs: re-generate x86_64 ABI compatibility CSV
This picks up the new EPYC-Genoa, SapphireRapids & GraniteRapids CPUs, removes the now deleted Icelake-Client CPU, and adds the newer versions of many existing CPUs.
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
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86cf437d | 10-May-2023 |
Daniel P. Berrangé <berrange@redhat.com> |
docs: fix highlighting of CPU ABI header rows
The 'header-rows' directive indicates how many rows in the generated table are to be highlighted as headers. We only have one such row in the CSV file i
docs: fix highlighting of CPU ABI header rows
The 'header-rows' directive indicates how many rows in the generated table are to be highlighted as headers. We only have one such row in the CSV file included. This removes the accident bold highlighting of the 'i486' CPU model.
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
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28004fb7 | 29-Jan-2024 |
Rayhan Faizel <rayhan.faizel@gmail.com> |
hw/ssi: Implement BCM2835 SPI Controller
This patch adds the SPI controller for the BCM2835. Polling and interrupt modes of transfer are supported. DMA and LoSSI modes are currently unimplemented.
hw/ssi: Implement BCM2835 SPI Controller
This patch adds the SPI controller for the BCM2835. Polling and interrupt modes of transfer are supported. DMA and LoSSI modes are currently unimplemented.
Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com> Message-id: 20240129221807.2983148-2-rayhan.faizel@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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1eeb432a | 30-Jan-2024 |
David Woodhouse <dwmw@amazon.co.uk> |
doc/sphinx/hxtool.py: add optional label argument to SRST directive
We can't just embed labels directly into files like qemu-options.hx which are included from multiple top-level rST files, because
doc/sphinx/hxtool.py: add optional label argument to SRST directive
We can't just embed labels directly into files like qemu-options.hx which are included from multiple top-level rST files, because Sphinx sees the labels as duplicate: https://github.com/sphinx-doc/sphinx/issues/9707
So add an optional argument to the SRST directive which causes a label of the form '.. _DOCNAME-HXFILE-LABEL:' to be emitted, where 'DOCNAME' is the name of the top level rST file, 'HXFILE' is the filename of the .hx file, and 'LABEL' is the text provided within the 'SRST()' directive. Using the DOCNAME of the top-level rST document means that it is unique even when the .hx file is included from two different documents, as is the case for qemu-options.hx
Now where the Xen PV documentation refers to the documentation for the -initrd command line option, it can emit a link directly to it as '<system/invocation-qemu-options-initrd>'.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Paul Durrant <paul@xen.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240130190348.682912-1-dwmw2@infradead.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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db101376 | 22-Jan-2024 |
Yihuan Pan <xun794@gmail.com> |
qemu-docs: Update options for graphical frontends
The command line options `-ctrl-grab` and `-alt-grab` have been removed in QEMU 7.1. Instead, use the `-display sdl,grab-mod=<modifiers>` option to
qemu-docs: Update options for graphical frontends
The command line options `-ctrl-grab` and `-alt-grab` have been removed in QEMU 7.1. Instead, use the `-display sdl,grab-mod=<modifiers>` option to specify the grab modifiers.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2103 Signed-off-by: Yihuan Pan <xun794@gmail.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
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1acf2159 | 22-Jan-2024 |
Gustavo Romero <gustavo.romero@linaro.org> |
docs/system/arm/virt.rst: Add note on CPU features off by default
Add a note on CPU features that are off by default in `virt` machines. Some CPU features will remain off even if a CPU-capable CPU (
docs/system/arm/virt.rst: Add note on CPU features off by default
Add a note on CPU features that are off by default in `virt` machines. Some CPU features will remain off even if a CPU-capable CPU (e.g., `-cpu max`) is selected because they require support in both the CPU itself and in the wider system. Therefore, the user, besides selecting a CPU that supports such features, must also turn on the feature using a machine option.
Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Message-id: 20240122211215.95073-1-gustavo.romero@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2af71d28 | 15-Jan-2024 |
Guenter Roeck <linux@roeck-us.net> |
hw/arm: Add watchdog timer to Allwinner H40 and Bananapi board
Add watchdog timer support to Allwinner-H40 and Bananapi. The watchdog timer is added as an overlay to the Timer module memory map.
Si
hw/arm: Add watchdog timer to Allwinner H40 and Bananapi board
Add watchdog timer support to Allwinner-H40 and Bananapi. The watchdog timer is added as an overlay to the Timer module memory map.
Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> Message-id: 20240115182757.1095012-4-linux@roeck-us.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2a02da74 | 15-Jan-2024 |
Guenter Roeck <linux@roeck-us.net> |
hw/arm: Add AHCI/SATA controller to Allwinner R40 and Bananapi board
Allwinner R40 supports an AHCI compliant SATA controller. Add support for it.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro
hw/arm: Add AHCI/SATA controller to Allwinner R40 and Bananapi board
Allwinner R40 supports an AHCI compliant SATA controller. Add support for it.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Message-id: 20240115182757.1095012-3-linux@roeck-us.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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43eef24f | 15-Jan-2024 |
Guenter Roeck <linux@roeck-us.net> |
hw/arm: Add EHCI/OHCI controllers to Allwinner R40 and Bananapi board
Allwinner R40 supports two USB host ports shared between a USB 2.0 EHCI host controller and a USB 1.1 OHCI host controller. Add
hw/arm: Add EHCI/OHCI controllers to Allwinner R40 and Bananapi board
Allwinner R40 supports two USB host ports shared between a USB 2.0 EHCI host controller and a USB 1.1 OHCI host controller. Add support for both of them.
If machine USB support is not enabled, create unimplemented devices for the USB memory ranges to avoid crashes when booting Linux.
Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240115182757.1095012-2-linux@roeck-us.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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20936684 | 09-Jan-2024 |
Inès Varhol <ines.varhol@telecom-paris.fr> |
hw/misc: Implement STM32L4x5 SYSCFG
Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@teleco
hw/misc: Implement STM32L4x5 SYSCFG
Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Message-id: 20240109194438.70934-2-ines.varhol@telecom-paris.fr Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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c9948fdd | 09-Jan-2024 |
Inès Varhol <ines.varhol@telecom-paris.fr> |
hw/misc: Implement STM32L4x5 EXTI
Although very similar to the STM32F4xx EXTI, STM32L4x5 EXTI generates more than 32 event/interrupt requests and thus uses more registers than STM32F4xx EXTI which g
hw/misc: Implement STM32L4x5 EXTI
Although very similar to the STM32F4xx EXTI, STM32L4x5 EXTI generates more than 32 event/interrupt requests and thus uses more registers than STM32F4xx EXTI which generates 23 event/interrupt requests.
Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240109160658.311932-2-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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8cf1da72 | 09-Jan-2024 |
Peter Maydell <peter.maydell@linaro.org> |
docs/system/arm/virt.rst: Improve 'highmem' option docs
Improve the 'highmem' option docs to note that by default we assume that a 32-bit kernel on an LPAE-capable CPU has LPAE enabled, and what the
docs/system/arm/virt.rst: Improve 'highmem' option docs
Improve the 'highmem' option docs to note that by default we assume that a 32-bit kernel on an LPAE-capable CPU has LPAE enabled, and what the consequences are.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20240109170834.1387457-1-peter.maydell@linaro.org
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e0299f71 | 04-Jan-2024 |
Bin Meng <bmeng@tinylab.org> |
docs/system/riscv: sifive_u: Update S-mode U-Boot image build instructions
Currently, the documentation outlines the process for building the S-mode U-Boot image using `make menuconfig` and manual a
docs/system/riscv: sifive_u: Update S-mode U-Boot image build instructions
Currently, the documentation outlines the process for building the S-mode U-Boot image using `make menuconfig` and manual actions within the menuconfig UI. However, this approach is fragile due to Kconfig options potentially changing across different releases. For example, CONFIG_OF_PRIOR_STAGE has been replaced by CONFIG_BOARD since v2022.01 release, and CONFIG_TEXT_BASE has been moved to the 'General setup' menu from the 'Boot options' menu in v2024.01 release.
This update aims to make the S-mode U-Boot image build instructions future-proof. It leverages the 'config' script provided in the U-Boot source tree to edit the .config file, followed by a `make olddefconfig`.
Validated with U-Boot v2024.01 release.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240104071523.273702-1-bmeng@tinylab.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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60db7a03 | 20-Dec-2023 |
Heinrich Schuchardt <heinrich.schuchardt@canonical.com> |
docs/system/riscv: document acpi parameter of virt machine
Since QEMU v8.0.0 the RISC-V virt machine has a switch to disable ACPI table generation. Add it to the documentation.
Fixes: 168b8c29cedb
docs/system/riscv: document acpi parameter of virt machine
Since QEMU v8.0.0 the RISC-V virt machine has a switch to disable ACPI table generation. Add it to the documentation.
Fixes: 168b8c29cedb ("hw/riscv/virt: Add a switch to disable ACPI") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20231220193436.25909-1-heinrich.schuchardt@canonical.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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e2862554 | 09-Jan-2024 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Add FEAT_NV2 to max, neoverse-n2, neoverse-v1 CPUs
Enable FEAT_NV2 on the 'max' CPU, and stop filtering it out for the Neoverse N2 and Neoverse V1 CPUs.
Signed-off-by: Peter Maydell <pe
target/arm: Add FEAT_NV2 to max, neoverse-n2, neoverse-v1 CPUs
Enable FEAT_NV2 on the 'max' CPU, and stop filtering it out for the Neoverse N2 and Neoverse V1 CPUs.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Miguel Luis <miguel.luis@oracle.com>
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1274a47f | 09-Jan-2024 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Add FEAT_NV to max, neoverse-n2, neoverse-v1 CPUs
Enable FEAT_NV on the 'max' CPU, and stop filtering it out for the Neoverse N2 and Neoverse V1 CPUs. We continue to downgrade FEAT_NV2
target/arm: Add FEAT_NV to max, neoverse-n2, neoverse-v1 CPUs
Enable FEAT_NV on the 'max' CPU, and stop filtering it out for the Neoverse N2 and Neoverse V1 CPUs. We continue to downgrade FEAT_NV2 support to FEAT_NV for the latter two CPU types.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Miguel Luis <miguel.luis@oracle.com>
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41581f13 | 08-Jan-2024 |
Inès Varhol <ines.varhol@telecom-paris.fr> |
hw/arm: Add minimal support for the B-L475E-IOT01A board
This commit adds a new B-L475E-IOT01A board using the STM32L475VG SoC as well as a dedicated documentation file. The implementation is derive
hw/arm: Add minimal support for the B-L475E-IOT01A board
This commit adds a new B-L475E-IOT01A board using the STM32L475VG SoC as well as a dedicated documentation file. The implementation is derived from the Netduino Plus 2 machine. There are no peripherals implemented yet, only memory regions.
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Message-id: 20240108135849.351719-3-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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8a780cd2 | 03-Jan-2024 |
Samuel Tardieu <sam@rfc1149.net> |
docs: use "buses" rather than "busses"
If "busses" might be encountered as a plural of "bus" (5 instances), the correct spelling is "buses" (26 instances). Fixing those 5 instances makes the doc mor
docs: use "buses" rather than "busses"
If "busses" might be encountered as a plural of "bus" (5 instances), the correct spelling is "buses" (26 instances). Fixing those 5 instances makes the doc more consistent.
Signed-off-by: Samuel Tardieu <sam@rfc1149.net> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
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fd49b215 | 13-Dec-2023 |
Yihuan Pan <xun794@gmail.com> |
qemu-options: Clarify handling of commas in options parameters
Provide explicit guidance on dealing with option parameters as arbitrary strings containing commas, such as in "file=my,file" and "stri
qemu-options: Clarify handling of commas in options parameters
Provide explicit guidance on dealing with option parameters as arbitrary strings containing commas, such as in "file=my,file" and "string=a,b". The updated documentation emphasizes the need to double commas when they appear within such parameters.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1839 Signed-off-by: Yihuan Pan <xun794@gmail.com> Message-ID: <20231213141706.629833-2-xun794@gmail.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
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