| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/sim/axi/ |
| H A D | sim_axi4_lib.svh | 27 interface axi4_wdata_t #(parameter DWIDTH=64) constant
56 interface axi4_rdata_t #(parameter DWIDTH=64, parameter IDWIDTH=4) constant
72 interface axi4_wr_t #(parameter DWIDTH=64, parameter AWIDTH=32, parameter IDWIDTH=4) constant
84 interface axi4_rd_t #(parameter DWIDTH=64, parameter AWIDTH=32, parameter IDWIDTH=4) constant
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| H A D | sim_axis_lib.svh | 7 interface axis_t #(parameter DWIDTH = 32, parameter NUM_STREAMS = 1)(input clk); constant
27 interface axis_master #(parameter DWIDTH = 32, parameter NUM_STREAMS = 1)(input clk); constant
122 interface axis_slave #(parameter DWIDTH = 32, parameter NUM_STREAMS = 1)(input clk); constant
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| /dports/devel/nextpnr/nextpnr-48cd407/tests/ice40/regressions/issue0148/hdl/cpu/ |
| H A D | alu.v | 7 parameter DWIDTH = 16, constant
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| H A D | regfile.v | 8 parameter DWIDTH = 16 constant
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/xge/rtl/verilog/ |
| H A D | meta_sync.v | 46 parameter DWIDTH = 1; constant
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| H A D | generic_mem_medium.v | 58 parameter DWIDTH = 32; constant
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| H A D | generic_mem_small.v | 59 parameter DWIDTH = 32; constant
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| H A D | generic_mem_xilinx_block.v | 58 parameter DWIDTH = 32; constant
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| /dports/cad/ghdl/ghdl-1.0.0/testsuite/synth/issue1318/ |
| H A D | ram_blk.vhdl | 8 DWIDTH : integer := 64 generic
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/wishbone/ |
| H A D | settings_readback.v | 16 #(parameter AWIDTH=16, parameter DWIDTH=32, parameter RB_ADDRW=2) constant
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| H A D | settings_bus.v | 13 #(parameter AWIDTH=16, parameter DWIDTH=32, parameter SWIDTH=8) constant
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| /dports/devel/nextpnr/nextpnr-48cd407/tests/ice40/regressions/issue0148/hdl/vga/ |
| H A D | videoram.v | 8 module videoram #(parameter DWIDTH=16, parameter AWIDTH=8) ( constant
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/control_lib/ |
| H A D | settings_bus.v | 22 #(parameter AWIDTH=16, parameter DWIDTH=32) constant
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| H A D | ram_2port.v | 21 #(parameter DWIDTH=32, constant
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/fosphor/ |
| H A D | f15_line_mem.v | 22 parameter integer DWIDTH = 18 constant
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/crossbar/synth/ |
| H A D | chdr_crossbar_nxn_top.v.in | 13 localparam DWIDTH = {dataw}; constant
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| H A D | axis_ctrl_crossbar_nxn_top.v.in | 14 localparam DWIDTH = {dataw}; constant
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/control/ |
| H A D | settings_bus_mux.v | 12 parameter DWIDTH=32, constant
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| H A D | regport_to_settingsbus.v | 19 parameter DWIDTH = 32, constant
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| H A D | ram_2port_impl.vh | 11 parameter DWIDTH = 32, // Width of the memory block constant
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/ |
| H A D | ram_to_fifo.v | 14 #(parameter DWIDTH=32, constant
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| /dports/math/visualpolylib/visualpolylib.0.9e/ |
| H A D | gtk_repere.h | 23 #define DWIDTH (Width-DOMAIN_BORD) macro
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| /dports/cad/verilator/verilator-4.216/test_regress/t/ |
| H A D | t_interface_param2.v | 18 interface simple_bus #(AWIDTH = 8, DWIDTH = 8) constant
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/utils/ |
| H A D | axis_ctrlport_reg.v | 42 parameter DWIDTH = 32, constant
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/sim/general/ |
| H A D | sim_file_io.svh | 30 parameter DWIDTH = 64 constant
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