| /dragonfly/sys/dev/drm/i915/ |
| H A D | intel_dpll_mgr.c | 101 struct intel_shared_dpll *pll) in intel_get_shared_dpll_id()
112 struct intel_shared_dpll *pll, in assert_shared_dpll()
249 struct intel_shared_dpll *pll; in intel_find_shared_dpll() local
322 struct intel_shared_dpll *pll; in intel_shared_dpll_swap_state() local
423 struct intel_shared_dpll *pll; in ibx_get_dpll() local
755 struct intel_shared_dpll *pll; in hsw_ddi_hdmi_get_dpll() local
780 struct intel_shared_dpll *pll; in hsw_ddi_dp_get_dpll() local
810 struct intel_shared_dpll *pll; in hsw_get_dpll() local
1365 struct intel_shared_dpll *pll; in skl_get_dpll() local
1812 struct intel_shared_dpll *pll; in bxt_get_dpll() local
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| H A D | intel_ddi.c | 900 static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) in hsw_pll_to_ddi_pll_sel()
1409 u32 val, pll; in hsw_ddi_clock_get() local
1454 struct intel_shared_dpll *pll; in bxt_calc_pll_link() local
2122 const struct intel_shared_dpll *pll) in intel_ddi_clk_select()
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| H A D | intel_display.c | 8631 struct intel_shared_dpll *pll; in ironlake_get_pipe_config() local
9116 struct intel_shared_dpll *pll; in haswell_get_ddi_port_state() local
11611 struct intel_shared_dpll *pll, in verify_single_dpll_state()
11679 struct intel_shared_dpll *pll = old_state->shared_dpll; in verify_shared_dpll_state() local
14956 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; in intel_modeset_readout_hw_state() local
15131 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; in intel_modeset_setup_hw_state() local
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| H A D | i915_reg.h | 154 #define _PLL(pll, a, b) ((a) + (pll)*((b)-(a))) argument
155 #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) argument
7255 #define PCH_DPLL(pll) _MMIO(pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) argument
7262 #define PCH_FP0(pll) _MMIO(pll == 0 ? _PCH_FPA0 : _PCH_FPB0) argument
7263 #define PCH_FP1(pll) _MMIO(pll == 0 ? _PCH_FPA1 : _PCH_FPB1) argument
8442 #define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2) argument
8466 #define PORT_CLK_SEL_WRPLL(pll) (((pll)+4)<<29) argument
8604 #define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << ((port)*2)) argument
8613 #define CNL_DPLL_ENABLE(pll) _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE) argument
8632 #define CNL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0) argument
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| /dragonfly/sys/dev/netif/ath/ath_hal/ar9001/ |
| H A D | ar9130_phy.c | 34 uint32_t pll; in ar9130InitPLL() local
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| H A D | ar9160_attach.c | 92 uint32_t pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); in ar9160InitPLL() local
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| /dragonfly/sys/dev/drm/amd/amdgpu/ |
| H A D | amdgpu_pll.c | 114 void amdgpu_pll_compute(struct amdgpu_pll *pll, in amdgpu_pll_compute()
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| H A D | atombios_crtc.c | 827 struct amdgpu_pll *pll; in amdgpu_atombios_crtc_set_pll() local
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| H A D | dce_v10_0.c | 2218 int pll; in dce_v10_0_pick_pll() local
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| H A D | dce_v11_0.c | 2251 int pll; in dce_v11_0_pick_pll() local
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| /dragonfly/sys/dev/powermng/powernow/ |
| H A D | powernow.c | 103 unsigned int pll; member
119 uint8_t pll; member
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| /dragonfly/sys/dev/drm/radeon/ |
| H A D | radeon_legacy_tv.c | 242 struct radeon_pll *pll; in radeon_legacy_tv_get_std_mode() local
434 struct radeon_pll *pll; in radeon_legacy_tv_init_restarts() local
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| H A D | radeon_display.c | 949 void radeon_compute_pll_avivo(struct radeon_pll *pll, in radeon_compute_pll_avivo()
1102 void radeon_compute_pll_legacy(struct radeon_pll *pll, in radeon_compute_pll_legacy()
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| H A D | atombios_crtc.c | 1070 struct radeon_pll *pll; in atombios_crtc_set_pll() local
1867 int pll; in radeon_atom_pick_pll() local
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| H A D | radeon_legacy_crtc.c | 754 struct radeon_pll *pll; in radeon_set_pll() local
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| /dragonfly/sys/dev/netif/ath/ath_hal/ar9002/ |
| H A D | ar9280_attach.c | 107 uint32_t pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); in ar9280InitPLL() local
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| /dragonfly/sys/dev/crypto/hifn/ |
| H A D | hifn7751.c | 300 hifn_getpllconfig(device_t dev, u_int *pll) in hifn_getpllconfig()
1214 u_int32_t pll; in hifn_init_pci_registers() local
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| /dragonfly/sys/dev/netif/bwn/siba/ |
| H A D | siba_core.c | 1130 uint32_t bufsth = 0, pll, pmu; in siba_cc_pmu1_pll0_init() local
1212 uint32_t pmu, tmp, pll; in siba_cc_pmu0_pll0_init() local
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| /dragonfly/sys/bus/cam/scsi/ |
| H A D | scsi_ch.h | 290 u_int8_t pll[2]; /* parameter list length */ member
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| /dragonfly/sys/dev/netif/ath/ath_hal/ar5416/ |
| H A D | ar5416_reset.c | 1503 uint32_t pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; in ar5416InitPLL() local
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| /dragonfly/sys/contrib/dev/ath/ath_hal/ar9300/ |
| H A D | ar9300_reset.c | 1367 u_int32_t pll; in ar9300_init_pll() local
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