| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/packet_proc/ |
| H A D | axis_to_cvita.v | 12 input wire [63:0] s_axis_tdata, port
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| H A D | arm_deframer.v | 23 input wire [63:0] s_axis_tdata, port
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/crossbar/ |
| H A D | axis_port_terminator.v | 17 input wire [DATA_W-1:0] s_axis_tdata, // Input data port
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| H A D | axis_ctrl_crossbar_nxn.v | 44 input wire [(NPORTS*WIDTH)-1:0] s_axis_tdata, port
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| H A D | axis_ingress_vc_buff.v | 20 input wire [WIDTH-1:0] s_axis_tdata, port
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| H A D | axis_switch.v | 25 input wire [(DATA_W*IN_PORTS)-1:0] s_axis_tdata, // Input data port
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/crossbar/synth/ |
| H A D | chdr_crossbar_nxn_top.v.in | 18 (* dont_touch = "true"*) wire [(DWIDTH*NPORTS)-1:0] s_axis_tdata , m_axis_tdata ; net
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| H A D | axis_ctrl_crossbar_nxn_top.v.in | 18 (* dont_touch = "true"*) wire [(DWIDTH*NPORTS)-1:0] s_axis_tdata , m_axis_tdata ; net
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/ |
| H A D | datapath_gatekeeper.v | 22 input wire [WIDTH-1:0] s_axis_tdata, port
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/utils/ |
| H A D | chdr_pad_packet.v | 28 input wire [CHDR_W-1:0] s_axis_tdata, port
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| H A D | chdr_trim_payload.v | 26 input wire [CHDR_W-1:0] s_axis_tdata, port
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/xge_interface/ |
| H A D | axi64_to_xge64.v | 21 input [63:0] s_axis_tdata, port
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/axi/ |
| H A D | axis_split.v | 37 input wire [DATA_W-1:0] s_axis_tdata, port
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| H A D | axis_upsizer.v | 33 input wire [IN_DATA_W-1:0] s_axis_tdata, // Input stream tdata port
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| H A D | axis_downsizer.v | 33 input wire [(OUT_DATA_W*RATIO)-1:0] s_axis_tdata, // Input stream tdata port
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| H A D | axis_packet_flush.v | 45 input wire [WIDTH-1:0] s_axis_tdata, port
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/packet_proc/arp_responder/test/ |
| H A D | arp_responder_test.vhd | 25 signal s_axis_tdata : std_logic_vector(63 downto 0); signal
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/sim/chdr_stream_endpoint_tb/ |
| H A D | lossy_xport_model.v | 14 input wire [CHDR_W-1:0] s_axis_tdata, port
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/sim/fifo/axi_fifo_2clk/ |
| H A D | axi_fifo_2clk_tb.sv | 12 reg [WIDTH-1:0] s_axis_tdata; register
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/packet_proc/arp_responder/ |
| H A D | arp_responder.vhd | 27 s_axis_tdata : in std_logic_vector(63 downto 0); port
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/ |
| H A D | rfnoc_fir_filter_core.v | 86 input wire [DATA_W-1:0] s_axis_tdata, port
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/crossbar/crossbar_tb/ |
| H A D | chdr_traffic_sink_sim.sv | 38 input [WIDTH-1:0] s_axis_tdata, port
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/core/ |
| H A D | chdr_data_swapper.v | 39 input wire [CHDR_W-1:0] s_axis_tdata, port
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_keep_one_in_n/ |
| H A D | rfnoc_keep_one_in_n.v | 23 input wire [WIDTH-1:0] s_axis_tdata, port
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/fifo/ |
| H A D | fifo64_to_axi4lite.v | 41 input [63:0] s_axis_tdata, port
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