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Searched defs:tCWL (Results 1 – 8 of 8) sorted by relevance

/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/Protocol/
H A DMemInfo.h70 …UINT16 tCWL; ///< Offset 8 Number of tCK cycles for the channel DIMM's minimum CAS write latenc… member
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/
H A DMemInfo.h71 …UINT16 tCWL; ///< Offset 8 Number of tCK cycles for the channel DIMM's minimum CAS write latenc… member
/dports/databases/litestream/litestream-0.3.6/vendor/cloud.google.com/go/pubsublite/internal/wire/
H A Dresources.go132 return LocationPath{Project: s.Project, Zone: s.Zone}
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/
H A DMemInfoHob.h131 UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. member
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/
H A DMemInfoHob.h122 UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. member
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/
H A Dmeminit.c496 uint8_t tCWL; in ddrphy_init() local
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/MemoryInit/Include/
H A DMrcInterface.h758 UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. member
1302 …UINT16 tCWL; ///< Offset 48 User defined Memory Timing tCWL value, valid when … member
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Include/Coffeelake/
H A DMrcSpdData.h736 } SPD_MODULE_REVISION_CODE;