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Searched refs:s (Results 101 – 125 of 2058) sorted by relevance

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/qemu/hw/net/
H A Dopencores_eth.c85 memset(s->regs, 0, sizeof(s->regs)); in mii_reset()
94 mii_set_link(s, s->link_ok); in mii_reset()
295 return s->desc + s->rx_desc; in rx_desc()
300 return s->desc + s->tx_desc; in tx_desc()
318 open_eth_update_irq(s, old_val & s->regs[INT_MASK], in open_eth_int_source_write()
319 s->regs[INT_SOURCE] & s->regs[INT_MASK]); in open_eth_int_source_write()
336 memset(s->regs, 0, sizeof(s->regs)); in open_eth_reset()
461 s->rx_desc = s->regs[TX_BD_NUM];
524 if (s->tx_desc >= s->regs[TX_BD_NUM]) {
590 s->rx_desc = s->regs[TX_BD_NUM];
[all …]
H A Dimx_fec.c291 s = s->phy_consumer; in imx_phy_read()
360 s = s->phy_consumer; in imx_phy_write()
460 if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] & in imx_eth_update()
656 memset(s->regs, 0, sizeof(s->regs)); in imx_eth_reset()
662 s->regs[ENET_PALR] = (s->conf.macaddr.a[0] << 24) in imx_eth_reset()
936 s->rx_descriptor = s->regs[ENET_RDSR]; in imx_eth_write()
940 s->tx_descriptor[0] = s->regs[ENET_TDSR]; in imx_eth_write()
1012 s->rx_descriptor = s->regs[index]; in imx_eth_write()
1020 s->tx_descriptor[0] = s->regs[index]; in imx_eth_write()
1031 s->tx_descriptor[1] = s->regs[index]; in imx_eth_write()
[all …]
H A Di82596.c184 memset(&s->mult[0], 0, sizeof(s->mult)); in set_multicast_list()
213 s->scb_status = (s->scb_status & 0xf000) in update_scb_status()
214 | (s->cu_status << 8) | (s->rx_status << 4); in update_scb_status()
215 set_uint16(s->scb, s->scb_status); in update_scb_status()
228 s->ca = s->ca_active = 0; in i82596_s_reset()
254 set_individual_address(s, s->cmd_p); in command_loop()
274 set_uint32(s->cmd_p + 8, s->lnkst); in command_loop()
277 i82596_transmit(s, s->cmd_p); in command_loop()
280 set_multicast_list(s, s->cmd_p); in command_loop()
393 s->cmd_p = get_uint32(s->scb + 4); in examine_scb()
[all …]
H A Drtl8139.c814 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, in rtl8139_can_receive()
1134 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize); in rtl8139_do_receive()
1144 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8); in rtl8139_do_receive()
1168 s->RxBufAddr = MOD2(RX_ALIGN(s->RxBufAddr), s->RxBufferSize); in rtl8139_do_receive()
1173 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr); in rtl8139_do_receive()
1218 memcpy(s->phys, s->conf.macaddr.a, 6); in rtl8139_reset()
1384 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize); in rtl8139_RxBufferEmpty()
2533 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr); in rtl8139_RxBufPtr_write()
3133 s->cplus_enabled = s->CpCmd != 0; in rtl8139_post_load()
3369 memory_region_init_io(&s->bar_io, OBJECT(s), &rtl8139_io_ops, s, in pci_rtl8139_realize()
[all …]
H A Deepro100.c408 s->scb_stat &= ~s->mem[SCBAck]; in eepro100_acknowledge()
409 s->mem[SCBAck] = s->scb_stat; in eepro100_acknowledge()
710 pci_dma_write(&s->dev, s->statsaddr, &s->statistics, s->stats_size); in dump_statistics()
730 pci_dma_read(&s->dev, s->cb_address, &s->tx, sizeof(s->tx)); in read_cb()
853 s->cb_address = s->cu_base + s->cu_offset; in action_command()
869 s->cu_offset = s->tx.link; in action_command()
872 s->tx.status, s->tx.command, s->tx.link)); in action_command()
1720 pci_dma_read(&s->dev, s->ru_base + s->ru_offset, in nic_receive()
1737 stw_le_pci_dma(&s->dev, s->ru_base + s->ru_offset + in nic_receive()
1739 stw_le_pci_dma(&s->dev, s->ru_base + s->ru_offset + in nic_receive()
[all …]
/qemu/hw/misc/
H A Dmps2-scc.c66 return scc_partno(s) == 0x524 || scc_partno(s) == 0x547 || in have_cfg2()
73 return scc_partno(s) != 0x524 && scc_partno(s) != 0x547 && in have_cfg3()
80 return scc_partno(s) == 0x524 || scc_partno(s) == 0x547 || in have_cfg5()
87 return scc_partno(s) == 0x524 || scc_partno(s) == 0x536; in have_cfg6()
257 qemu_set_irq(s->remap, s->cfg0 & 1); in mps2_scc_write()
366 s->cfg0 = s->cfg0_reset; in mps2_scc_reset()
367 s->cfg1 = 0; in mps2_scc_reset()
368 s->cfg2 = 0; in mps2_scc_reset()
369 s->cfg5 = 0; in mps2_scc_reset()
377 s->oscclk[i] = s->oscclk_reset[i]; in mps2_scc_reset()
[all …]
H A Dapplesmc.c173 s->key[s->read_pos] = val; in applesmc_io_data_write()
185 s->key[0], s->key[1], s->key[2], s->key[3]); in applesmc_io_data_write()
214 if (s->data_pos < s->data_len) { in applesmc_io_data_read()
215 s->last_ret = s->data[s->data_pos]; in applesmc_io_data_read()
217 s->key[0], s->key[1], s->key[2], s->key[3], in applesmc_io_data_read()
220 if (s->data_pos == s->data_len) { in applesmc_io_data_read()
223 s->key[0], s->key[1], s->key[2], s->key[3], in applesmc_io_data_read()
312 memory_region_init_io(&s->io_data, OBJECT(s), &applesmc_data_io_ops, s, in applesmc_isa_realize()
317 memory_region_init_io(&s->io_cmd, OBJECT(s), &applesmc_cmd_io_ops, s, in applesmc_isa_realize()
322 memory_region_init_io(&s->io_err, OBJECT(s), &applesmc_err_io_ops, s, in applesmc_isa_realize()
[all …]
/qemu/hw/i2c/
H A Dexynos4210_i2c.c115 s->i2cds = i2c_recv(s->bus); in exynos4210_i2c_data_receive()
125 if (i2c_send(s->bus, s->i2cds) < 0 && (s->i2ccon & I2CCON_ACK_GEN)) { in exynos4210_i2c_data_send()
181 s->i2ccon = (v & ~I2CCON_INT_PEND) | (s->i2ccon & I2CCON_INT_PEND); in exynos4210_i2c_write()
205 s->i2cstat = in exynos4210_i2c_write()
226 if (i2c_start_transfer(s->bus, s->i2cds >> 1, s->i2cds & 0x1) && in exynos4210_i2c_write()
258 s->i2clc = v; in exynos4210_i2c_write()
291 s->i2ccon = 0x00; in exynos4210_i2c_reset()
292 s->i2cstat = 0x00; in exynos4210_i2c_reset()
293 s->i2cds = 0xFF; in exynos4210_i2c_reset()
294 s->i2clc = 0x00; in exynos4210_i2c_reset()
[all …]
H A Dallwinner-i2c.c198 if (!allwinner_i2c_is_reset(s) && allwinner_i2c_bus_is_enabled(s)) { in allwinner_i2c_raise_interrupt()
216 value = s->addr; in allwinner_i2c_read()
226 s->data = i2c_recv(s->bus); in allwinner_i2c_read()
235 value = s->data; in allwinner_i2c_read()
256 value = s->ccr; in allwinner_i2c_read()
262 value = s->efr; in allwinner_i2c_read()
265 value = s->lcr; in allwinner_i2c_read()
307 if (i2c_start_transfer(s->bus, extract32(s->data, 1, 7), in allwinner_i2c_write()
323 if (i2c_send(s->bus, s->data)) { in allwinner_i2c_write()
361 if (!s->irq_clear_inverted && !(s->cntr & TWI_CNTR_INT_FLAG)) { in allwinner_i2c_write()
[all …]
H A Dimx_i2c.c97 if (imx_i2c_is_enabled(s) && imx_i2c_interrupt_is_enabled(s)) { in imx_i2c_raise_interrupt()
98 s->i2sr |= I2SR_IIF; in imx_i2c_raise_interrupt()
111 value = s->iadr; in imx_i2c_read()
114 value = s->ifdr; in imx_i2c_read()
117 value = s->i2cr; in imx_i2c_read()
120 value = s->i2sr; in imx_i2c_read()
184 s->iadr = iadr; in imx_i2c_write()
244 if (i2c_start_transfer(s->bus, extract32(s->i2dr_write, 1, 7), in imx_i2c_write()
249 s->address = s->i2dr_write; in imx_i2c_write()
254 if (i2c_send(s->bus, s->i2dr_write)) { in imx_i2c_write()
[all …]
/qemu/hw/display/
H A Dartist.c690 uint32_t color = (s->image_bitmap_op & 2) ? s->fg_color : s->bg_color; in font_write16()
934 vram_bit_write(s, s->vram_pos, s->vram_char_y++, val, size); in artist_reg_write()
939 s->vram_pos = vram_bit_write(s, s->vram_pos, s->vram_char_y, val, size); in artist_reg_write()
1107 font_write(s, s->font_write1); in artist_reg_write()
1113 font_write(s, s->font_write2); in artist_reg_write()
1318 framebuffer_update_display(surface, &s->fbsection, s->width, s->height, in artist_update_display()
1381 s->width = MIN(s->width, 2048); in artist_realizefn()
1382 s->height = MIN(s->height, 2048); in artist_realizefn()
1387 s->width = MAX(s->width, 640); in artist_realizefn()
1388 s->height = MAX(s->height, 480); in artist_realizefn()
[all …]
H A Dpxa2xx_lcd.c655 s->liidr = s->dma_ch[ch].id; in pxa2xx_dma_bs_set()
678 s->liidr = s->dma_ch[ch].id; in pxa2xx_dma_sof_set()
712 s->liidr = s->dma_ch[ch].id; in pxa2xx_dma_ber_set()
1137 framebuffer_update_display(surface, &s->fbsection, s->xres, s->yres, in pxa2xx_lcdc_dma0_redraw_rot0()
1166 framebuffer_update_display(surface, &s->fbsection, s->xres, s->yres, in pxa2xx_lcdc_dma0_redraw_rot90()
1198 framebuffer_update_display(surface, &s->fbsection, s->xres, s->yres, in pxa2xx_lcdc_dma0_redraw_rot180()
1229 framebuffer_update_display(surface, &s->fbsection, s->xres, s->yres, in pxa2xx_lcdc_dma0_redraw_rot270()
1271 s->transp = s->dma_ch[2].up || s->dma_ch[3].up; in pxa2xx_update_display()
1366 s->xres = s->yres = -1; in pxa2xx_lcdc_orientation()
1390 s->bpp = LCCR3_BPP(s->control[3]); in pxa2xx_lcdc_post_load()
[all …]
/qemu/hw/arm/
H A Dallwinner-h3.c277 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_H3_DEV_GIC_CPU]); in allwinner_h3_realize()
326 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_H3_DEV_PIT]); in allwinner_h3_realize()
348 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_DEV_CCU]); in allwinner_h3_realize()
360 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_DEV_SID]); in allwinner_h3_realize()
366 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, s->memmap[AW_H3_DEV_MMC0]); in allwinner_h3_realize()
370 object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0), in allwinner_h3_realize()
378 sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_H3_DEV_EMAC]); in allwinner_h3_realize()
434 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, s->memmap[AW_H3_DEV_RTC]); in allwinner_h3_realize()
438 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c0), 0, s->memmap[AW_H3_DEV_TWI0]); in allwinner_h3_realize()
443 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c1), 0, s->memmap[AW_H3_DEV_TWI1]); in allwinner_h3_realize()
[all …]
/qemu/net/
H A Dstream.c108 s->ioc_write_tag = qio_channel_add_watch(s->ioc, G_IO_OUT, in net_stream_receive()
112 s->send_index = 0; in net_stream_receive()
125 s->ioc_read_tag = qio_channel_add_watch(s->ioc, G_IO_IN, in net_stream_send_completed()
173 s->ioc = NULL; in net_stream_send()
201 if (s->addr) { in net_stream_cleanup()
205 if (s->ioc) { in net_stream_cleanup()
247 qio_net_listener_set_client_func(s->listener, NULL, s, NULL); in net_stream_listen()
369 s->ioc = NULL; in net_stream_client_connected()
378 s->timer_tag = 0; in net_stream_reconnect()
390 if (s->reconnect && s->timer_tag == 0) { in net_stream_arm_reconnect()
[all …]
/qemu/hw/gpio/
H A Dsifive_gpio.c27 pending = s->high_ip & s->high_ie; in update_output_irq()
28 pending |= s->low_ip & s->low_ie; in update_output_irq()
29 pending |= s->rise_ip & s->rise_ie; in update_output_irq()
30 pending |= s->fall_ip & s->fall_ie; in update_output_irq()
88 s->high_ip = deposit32(s->high_ip, i, 1, high_ip); in update_state()
91 s->low_ip = deposit32(s->low_ip, i, 1, low_ip); in update_state()
94 s->rise_ip = deposit32(s->rise_ip, i, 1, rise_ip); in update_state()
97 s->fall_ip = deposit32(s->fall_ip, i, 1, fall_ip); in update_state()
100 s->value = deposit32(s->value, i, 1, ival); in update_state()
294 s->in = deposit32(s->in, line, 1, value != 0); in sifive_gpio_set()
[all …]
H A Dstm32l4x5_gpio.c78 s->moder = s->moder_reset; in stm32l4x5_gpio_reset_hold()
80 s->ospeedr = s->ospeedr_reset; in stm32l4x5_gpio_reset_hold()
81 s->pupdr = s->pupdr_reset; in stm32l4x5_gpio_reset_hold()
114 trace_stm32l4x5_gpio_pins(s->name, s->disconnected_pins, in stm32l4x5_gpio_set()
183 trace_stm32l4x5_gpio_update_idr(s->name, old_idr, s->idr); in update_gpio_idr()
208 if (!(s->disconnected_pins & (1 << i)) && is_output(s, i)) { in get_gpio_pinmask_to_disconnect()
227 trace_stm32l4x5_gpio_pins(s->name, s->disconnected_pins, in disconnect_gpio_pins()
268 disconnect_gpio_pins(s, get_gpio_pinmask_to_disconnect(s)); in stm32l4x5_gpio_write()
276 disconnect_gpio_pins(s, get_gpio_pinmask_to_disconnect(s)); in stm32l4x5_gpio_write()
402 memory_region_init_io(&s->mmio, obj, &stm32l4x5_gpio_ops, s, in stm32l4x5_gpio_init()
[all …]
H A Dimx_gpio.c72 qemu_set_irq(s->irq[0], (s->isr & s->imr & 0x0000FFFF) ? 1 : 0); in imx_gpio_update_int()
73 qemu_set_irq(s->irq[1], (s->isr & s->imr & 0xFFFF0000) ? 1 : 0); in imx_gpio_update_int()
75 qemu_set_irq(s->irq[0], (s->isr & s->imr) ? 1 : 0); in imx_gpio_update_int()
91 s->isr = deposit32(s->isr, line, 1, 1); in imx_gpio_set_int_line()
104 s->isr = deposit32(s->isr, line, 1, 1); in imx_gpio_set_int_line()
117 s->psr = deposit32(s->psr, line, 1, imx_level); in imx_gpio_set()
160 reg_value = (s->dr & s->gdir) | (s->psr & ~s->gdir); in imx_gpio_read()
168 reg_value = s->psr & ~s->gdir; in imx_gpio_read()
229 s->icr = deposit64(s->icr, 0, 32, value); in imx_gpio_write()
234 s->icr = deposit64(s->icr, 32, 32, value); in imx_gpio_write()
[all …]
/qemu/hw/intc/
H A Dimx_avic.c63 uint64_t new = s->pending & s->enabled; in imx_avic_update()
81 if (imx_avic_prio(s, i) > s->intmask) { in imx_avic_update()
156 uint64_t flags = s->pending & s->enabled & ~s->is_fiq; in imx_avic_read()
177 uint64_t flags = s->pending & s->enabled & s->is_fiq; in imx_avic_read()
196 return (s->pending & s->enabled & ~s->is_fiq) >> 32; in imx_avic_read()
199 return (s->pending & s->enabled & ~s->is_fiq) & 0xffffffffULL; in imx_avic_read()
202 return (s->pending & s->enabled & s->is_fiq) >> 32; in imx_avic_read()
205 return (s->pending & s->enabled & s->is_fiq) & 0xffffffffULL; in imx_avic_read()
264 s->is_fiq = (s->is_fiq & 0xffffffffULL) | (val << 32); in imx_avic_write()
325 memset(s->prio, 0, sizeof s->prio); in imx_avic_reset()
[all …]
H A Darm_gic.c77 return s->revision == 2 || s->security_extn; in gic_has_groups()
171 qemu_irq *irq_lines = virt ? s->parent_virq : s->parent_irq; in gic_update_internal()
172 qemu_irq *fiq_lines = virt ? s->parent_vfiq : s->parent_fiq; in gic_update_internal()
520 uint32_t apr = s->apr[i][cpu] | s->nsapr[i][cpu]; in gic_get_prio_from_apr_bits()
552 s->h_apr[rcpu] &= s->h_apr[rcpu] - 1; in gic_drop_prio()
709 s->priority_mask[cpu] = pmask & gic_fullprio_mask(s, cpu); in gic_set_priority_mask()
847 group = gic_has_groups(s) && gic_test_group(s, irq, cpu); in gic_deactivate_irq()
923 group = gic_has_groups(s) && gic_test_group(s, irq, cpu); in gic_complete_irq()
1080 if (s->num_cpu == 1 && s->revision != REV_11MPCORE) { in gic_dist_readb()
1204 s->ctlr = deposit32(s->ctlr, 1, 1, value); in gic_dist_writeb()
[all …]
/qemu/util/
H A Dvfio-helpers.c172 s->device, s->bar_region_info[index].offset + offset); in qemu_vfio_pci_map_bar()
526 return s; in qemu_vfio_open_pci()
570 } else if (mid < &s->mappings[s->nr_mappings - 1] in qemu_vfio_find_mapping()
577 assert(mid < &s->mappings[s->nr_mappings]); in qemu_vfio_find_mapping()
603 s->mappings = g_renew(IOVAMapping, s->mappings, s->nr_mappings); in qemu_vfio_add_mapping()
657 s->mappings = g_renew(IOVAMapping, s->mappings, s->nr_mappings); in qemu_vfio_undo_mapping()
671 if (!(s->mappings[i].host + s->mappings[i].size <= in qemu_vfio_verify_mappings()
688 if (s->usable_iova_ranges[i].end < s->low_water_mark) { in qemu_vfio_find_fixed_iova()
738 if (s->high_water_mark - s->low_water_mark + 1 < size) { in qemu_vfio_water_mark_reached()
849 if (!s) { in qemu_vfio_close()
[all …]
/qemu/hw/sd/
H A Domap_mmc.c73 qemu_set_irq(s->irq, !!(s->status & s->mask)); in omap_mmc_interrupts_update()
344 return (s->dw << 15) | (s->mode << 12) | (s->enable << 11) | in omap_mmc_read()
361 i = s->fifo[s->fifo_start]; in omap_mmc_read()
387 return (s->cdet_wakeup << 2) | (s->cdet_enable) | s->sdio; in omap_mmc_read()
467 if (s->dw != 0 && s->lines < 4) in omap_mmc_write()
497 s->fifo[(s->fifo_start + s->fifo_len) & 31] = value; in omap_mmc_write()
506 s->blen_counter = s->blen; in omap_mmc_write()
511 s->nblk_counter = s->nblk; in omap_mmc_write()
512 s->blen_counter = s->blen; in omap_mmc_write()
644 sd_set_cb(s->card, NULL, s->cdet); in omap2_mmc_init()
[all …]
/qemu/hw/char/
H A Dcmsdk-apb-uart.c78 return s->bauddiv >= 16 && s->bauddiv <= s->pclk_frq; in uart_baudrate_ok()
93 ssp.speed = s->pclk_frq / s->bauddiv; in uart_update_parameters()
106 s->intstatus |= (s->state & (s->ctrl >> 2) & omask); in cmsdk_apb_uart_update()
108 qemu_set_irq(s->txint, !!(s->intstatus & R_INTSTATUS_TX_MASK)); in cmsdk_apb_uart_update()
109 qemu_set_irq(s->rxint, !!(s->intstatus & R_INTSTATUS_RX_MASK)); in cmsdk_apb_uart_update()
112 qemu_set_irq(s->uartint, !!(s->intstatus)); in cmsdk_apb_uart_update()
205 ret = qemu_chr_fe_write(&s->chr, &s->txbuf, 1); in uart_transmit()
313 s->state = 0; in cmsdk_apb_uart_reset()
314 s->ctrl = 0; in cmsdk_apb_uart_reset()
317 s->txbuf = 0; in cmsdk_apb_uart_reset()
[all …]
H A Dexynos4210_uart.c315 s->reg[I_(UINTP)] = s->reg[I_(UINTSP)] & ~s->reg[I_(UINTM)]; in exynos4210_uart_update_irq()
319 trace_exynos_uart_irq_raised(s->channel, s->reg[I_(UINTP)]); in exynos4210_uart_update_irq()
330 trace_exynos_uart_rx_timeout(s->channel, s->reg[I_(UTRSTAT)], in exynos4210_uart_timeout_int()
385 s->channel, speed, parity, data_bits, stop_bits, s->wordtime); in exynos4210_uart_update_parameters()
391 uint32_t timeout = ((s->reg[I_(UCON)] >> 12) & 0x0f) * s->wordtime; in exynos4210_uart_rx_timeout_set()
449 trace_exynos_uart_intclr(s->channel, s->reg[I_(UINTP)]); in exynos4210_uart_write()
493 s->reg[I_(UFSTAT)] = fifo_elements_number(&s->rx) & 0xff; in exynos4210_uart_read()
611 fifo_reset(&s->rx); in exynos4210_uart_reset()
612 fifo_reset(&s->tx); in exynos4210_uart_reset()
614 trace_exynos_uart_rxsize(s->channel, s->rx.size); in exynos4210_uart_reset()
[all …]
/qemu/hw/timer/
H A Di8254.c59 switch(s->mode) { in pit_get_count()
68 counter = s->count - ((2 * d) % s->count); in pit_get_count()
71 counter = s->count - (d % s->count); in pit_get_count()
113 s->count = val; in pit_load_count()
114 pit_irq_timer_update(s, s->count_load_time); in pit_load_count()
121 s->latched_count = pit_get_count(s); in pit_latch_count()
122 s->count_latched = s->rw_mode; in pit_latch_count()
187 pit_load_count(s, s->write_latch | (val << 8)); in pit_ioport_write()
259 if (!s->irq_timer || s->irq_disabled) { in pit_irq_timer_update()
281 pit_irq_timer_update(s, s->next_transition_time); in pit_irq_timer()
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H A Dcadence_ttc.c56 qemu_set_irq(s->irq, !!(s->reg_intr & s->reg_intr_en)); in cadence_timer_update()
151 timer_mod(s->timer, s->cpu_time + in cadence_timer_run()
166 if (!s->cpu_time_valid || old_time == s->cpu_time) { in cadence_timer_sync()
171 r = (int64_t)cadence_timer_get_steps(s, s->cpu_time - old_time); in cadence_timer_sync()
172 x = (int64_t)s->reg_value + ((s->reg_count & COUNTER_CTRL_DEC) ? -r : r); in cadence_timer_sync()
188 s->reg_intr |= (s->reg_count & COUNTER_CTRL_INT) ? in cadence_timer_sync()
256 s->reg_intr = 0; in cadence_ttc_read_imp()
371 s->reg_count = 0x21; in cadence_timer_reset()
377 s->freq = freq; in cadence_timer_init()
381 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cadence_timer_tick, s); in cadence_timer_init()
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