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/dports/devel/asl/asl-current/include/avr/
H A Dacm30.inc14 ACSR port 0x30 ; Config/Status Register
15 ACIS0 avrbit ACSR,0 ; Interrupt-Mode
16 ACIS1 avrbit ACSR,1
17 ACIC avrbit ACSR,2 ; Use Comparator as Capture Signal for Timer 1?
18 ACIE avrbit ACSR,3 ; Interrupt Enable
19 ACI avrbit ACSR,4 ; Interrupt Flag
20 ACO avrbit ACSR,5 ; Analog Comparator Output
21 ACBG avrbit ACSR,6 ; Bandgap Select
22 ACD avrbit ACSR,7 ; Disable
H A Dac90.inc14 ACSR port 0x08 ; Analog Comparator ControlStatus Register
15 ACIS0 avrbit ACSR,0 ; Interrupt-Mode
16 ACIS1 avrbit ACSR,1
18 ACIC avrbit ACSR,2 ; ...use Comparator as Capture Signal for Timer 1?
20 ACIE avrbit ACSR,3 ; Interrupt Enable
21 ACI avrbit ACSR,4 ; Interrupt Flag
22 ACO avrbit ACSR,5 ; Analog Comparator Output
23 ACD avrbit ACSR,7 ; Disable
H A Dregtn28.inc112 ACSR port 0x08 ; Analog Comparator Control and Status Register
113 ACIS0 avrbit ACSR,0 ; Interrupt-Mode
114 ACIS1 avrbit ACSR,1
115 ACIE avrbit ACSR,3 ; Interrupt Enable
116 ACI avrbit ACSR,4 ; Interrupt Flag
117 ACO avrbit ACSR,5 ; Analog Comparator Output
118 ACD avrbit ACSR,7 ; Disable
H A Dregtx459.inc181 ACSR port 0x1f ; Analog Comparator Control and Status Register
182 ACIS0 avrbit ACSR,0 ; Interrupt-Mode
183 ACIS1 avrbit ACSR,1
184 ACIC avrbit ACSR,2 ; Use Comparator As Capture Signal For Timer 0?
185 ACIE avrbit ACSR,3 ; Interrupt Enable
186 ACI avrbit ACSR,4 ; Interrupt Flag
187 ACO avrbit ACSR,5 ; Analog Comparator Output
188 ACD avrbit ACSR,7 ; Disable
H A Dregtnx7.inc246 ACSR port 0x30 ; Config/Status Register
247 ACIS0 avrbit ACSR,0 ; Interrupt-Mode
248 ACIS1 avrbit ACSR,1
249 ACIC avrbit ACSR,2 ; use Comparator as Capture Signal for Timer 1?
250 ACIE avrbit ACSR,3 ; Interrupt Enable
251 ACI avrbit ACSR,4 ; Interrupt Flag
252 ACO avrbit ACSR,5 ; Analog Comparator Output
253 ACIRS avrbit ACSR,6 ; Analog Comparator Internal Reference Select
254 ACD avrbit ACSR,7 ; Disable
H A Dacm.inc16 ACBG avrbit ACSR,6 ; Bandgap Select
H A Dacm2.inc16 AINBG avrbit ACSR,6 ; Bandgap Select
/dports/science/hypre/hypre-2.23.0/src/FEI_mv/fei-hypre/
H A DHYPRE_fei_matrix.cxx65 HYPRE_ParCSRMatrix ACSR; in HYPRE_FEMatrixGetObject() local
81 HYPRE_IJMatrixGetObject(A, (void **) &ACSR); in HYPRE_FEMatrixGetObject()
82 (*object) = (void *) ACSR; in HYPRE_FEMatrixGetObject()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/clk/pxa/
H A Dclk-pxa3xx.c103 unsigned long acsr = ACSR; in clk_pxa3xx_smemc_get_rate()
114 unsigned long acsr = ACSR; in pxa3xx_is_ring_osc_forced()
194 unsigned long acsr = ACSR; in clk_pxa3xx_system_bus_get_rate()
241 unsigned long acsr = ACSR; in clk_pxa3xx_run_get_rate()
257 unsigned long acsr = ACSR; in clk_pxa3xx_cpll_get_rate()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/clk/pxa/
H A Dclk-pxa3xx.c103 unsigned long acsr = ACSR; in clk_pxa3xx_smemc_get_rate()
114 unsigned long acsr = ACSR; in pxa3xx_is_ring_osc_forced()
194 unsigned long acsr = ACSR; in clk_pxa3xx_system_bus_get_rate()
241 unsigned long acsr = ACSR; in clk_pxa3xx_run_get_rate()
257 unsigned long acsr = ACSR; in clk_pxa3xx_cpll_get_rate()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/clk/pxa/
H A Dclk-pxa3xx.c103 unsigned long acsr = ACSR; in clk_pxa3xx_smemc_get_rate()
114 unsigned long acsr = ACSR; in pxa3xx_is_ring_osc_forced()
194 unsigned long acsr = ACSR; in clk_pxa3xx_system_bus_get_rate()
241 unsigned long acsr = ACSR; in clk_pxa3xx_run_get_rate()
257 unsigned long acsr = ACSR; in clk_pxa3xx_cpll_get_rate()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/cpufreq/
H A Dpxa3xx-cpufreq.c129 while ((ACSR & mask) != (accr & mask)) in __update_core_freq()
147 while ((ACSR & mask) != (accr & mask)) in __update_bus_freq()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/cpufreq/
H A Dpxa3xx-cpufreq.c129 while ((ACSR & mask) != (accr & mask)) in __update_core_freq()
147 while ((ACSR & mask) != (accr & mask)) in __update_bus_freq()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/cpufreq/
H A Dpxa3xx-cpufreq.c129 while ((ACSR & mask) != (accr & mask)) in __update_core_freq()
147 while ((ACSR & mask) != (accr & mask)) in __update_bus_freq()
/dports/lang/sdcc/sdcc-4.0.0/device/include/mcs51/
H A Dat89Sx051.h43 __sfr __at (0x97) ACSR ;
/dports/editors/fpc-ide/fpc-3.2.2/rtl/embedded/avr/
H A Dattiny28.pp18 ACSR : byte absolute $00+$28; // Analog Comparator Control And Status Register
55 // ACSR
/dports/lang/fpc-source/fpc-3.2.2/rtl/embedded/avr/
H A Dattiny28.pp18 ACSR : byte absolute $00+$28; // Analog Comparator Control And Status Register
55 // ACSR
/dports/lang/fpc/fpc-3.2.2/rtl/embedded/avr/
H A Dattiny28.pp18 ACSR : byte absolute $00+$28; // Analog Comparator Control And Status Register
55 // ACSR
/dports/lang/fpc-utils/fpc-3.2.2/rtl/embedded/avr/
H A Dattiny28.pp18 ACSR : byte absolute $00+$28; // Analog Comparator Control And Status Register
55 // ACSR
/dports/lang/sdcc/sdcc-4.0.0/sim/ucsim/avr.src/
H A Dregsavr.h49 #define ACSR 0x0028 macro
/dports/devel/avr-libc/avr-libc-2.0.0/include/avr/
H A Diotn11.h59 #define ACSR _SFR_IO8(0x08) macro
H A Dio1200.h59 #define ACSR _SFR_IO8(0x08) macro
H A Diotn12.h59 #define ACSR _SFR_IO8(0x08) macro
H A Diotn28.h70 #define ACSR _SFR_IO8(0x08) macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/arm/mach-pxa/include/mach/
H A Dpxa3xx-regs.h127 #define ACSR __REG(0x41340004) /* Application Subsystem Clock Status Register */ macro

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