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Searched refs:CPSR_AIF (Results 1 – 25 of 28) sorted by relevance

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/dports/emulators/py-unicorn/unicorn-1.0.2/qemu/target-arm/
H A Dcpu.h458 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) macro
461 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
H A Dhelper.c3057 | (env->GE << 16) | (env->daif & CPSR_AIF); in cpsr_read()
3084 env->daif &= ~(CPSR_AIF & mask); in cpsr_write()
3085 env->daif |= val & CPSR_AIF & mask; in cpsr_write()
/dports/emulators/unicorn/unicorn-1.0.2/qemu/target-arm/
H A Dcpu.h458 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) macro
461 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
H A Dhelper.c3057 | (env->GE << 16) | (env->daif & CPSR_AIF); in cpsr_read()
3084 env->daif &= ~(CPSR_AIF & mask); in cpsr_write()
3085 env->daif |= val & CPSR_AIF & mask; in cpsr_write()
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/arm/
H A Dinternals.h981 uint32_t valid = CPSR_M | CPSR_AIF | CPSR_IL | CPSR_NZCV; in aarch32_cpsr_valid_mask()
H A Dcpu.h1275 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) macro
1278 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
/dports/emulators/qemu60/qemu-6.0.0/target/arm/
H A Dinternals.h967 uint32_t valid = CPSR_M | CPSR_AIF | CPSR_IL | CPSR_NZCV; in aarch32_cpsr_valid_mask()
H A Dcpu.h1263 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) macro
1266 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/arm/
H A Dinternals.h1128 uint32_t valid = CPSR_M | CPSR_AIF | CPSR_IL | CPSR_NZCV; in aarch32_cpsr_valid_mask()
H A Dcpu.h1213 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) macro
1216 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
H A Dhelper.c8585 | (env->GE << 16) | (env->daif & CPSR_AIF); in cpsr_read()
8667 env->daif &= ~(CPSR_AIF & mask); in cpsr_write()
8668 env->daif |= val & CPSR_AIF & mask; in cpsr_write()
/dports/emulators/qemu/qemu-6.2.0/target/arm/
H A Dinternals.h989 uint32_t valid = CPSR_M | CPSR_AIF | CPSR_IL | CPSR_NZCV; in aarch32_cpsr_valid_mask()
H A Dcpu.h1275 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) macro
1278 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/arm/
H A Dinternals.h1128 uint32_t valid = CPSR_M | CPSR_AIF | CPSR_IL | CPSR_NZCV; in aarch32_cpsr_valid_mask()
H A Dcpu.h1213 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) macro
1216 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
H A Dhelper.c8584 | (env->GE << 16) | (env->daif & CPSR_AIF); in cpsr_read()
8666 env->daif &= ~(CPSR_AIF & mask); in cpsr_write()
8667 env->daif |= val & CPSR_AIF & mask; in cpsr_write()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/arm/
H A Dcpu.h1051 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) macro
1054 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
H A Dhelper.c6101 | (env->GE << 16) | (env->daif & CPSR_AIF); in cpsr_read()
6183 env->daif &= ~(CPSR_AIF & mask); in cpsr_write()
6184 env->daif |= val & CPSR_AIF & mask; in cpsr_write()
/dports/emulators/qemu5/qemu-5.2.0/target/arm/
H A Dinternals.h1169 uint32_t valid = CPSR_M | CPSR_AIF | CPSR_IL | CPSR_NZCV; in aarch32_cpsr_valid_mask()
H A Dcpu.h1245 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) macro
1248 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
H A Dhelper.c8745 | (env->GE << 16) | (env->daif & CPSR_AIF); in cpsr_read()
8827 env->daif &= ~(CPSR_AIF & mask); in cpsr_write()
8828 env->daif |= val & CPSR_AIF & mask; in cpsr_write()
/dports/emulators/qemu-utils/qemu-4.2.1/target/arm/
H A Dcpu.h1165 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) macro
1168 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
H A Dhelper.c7488 | (env->GE << 16) | (env->daif & CPSR_AIF); in cpsr_read()
7570 env->daif &= ~(CPSR_AIF & mask); in cpsr_write()
7571 env->daif |= val & CPSR_AIF & mask; in cpsr_write()
/dports/emulators/qemu42/qemu-4.2.1/target/arm/
H A Dcpu.h1165 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) macro
1168 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
H A Dhelper.c7488 | (env->GE << 16) | (env->daif & CPSR_AIF); in cpsr_read()
7570 env->daif &= ~(CPSR_AIF & mask); in cpsr_write()
7571 env->daif |= val & CPSR_AIF & mask; in cpsr_write()

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