| /dports/emulators/x49gp/x49gp/x49gp-code/qemu/qemu-git/target-arm/ |
| H A D | cpu.h | 245 #define CPSR_IT_0_1 (3 << 25) macro
253 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
290 if (mask & CPSR_IT_0_1) { in xpsr_write()
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| H A D | helper.c | 389 if (mask & CPSR_IT_0_1) { in cpsr_write()
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| /dports/emulators/py-unicorn/unicorn-1.0.2/qemu/target-arm/ |
| H A D | cpu.h | 451 #define CPSR_IT_0_1 (3U << 25) macro
460 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
575 if (mask & CPSR_IT_0_1) { in xpsr_write()
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| H A D | helper.c | 3072 if (mask & CPSR_IT_0_1) { in cpsr_write()
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| /dports/emulators/unicorn/unicorn-1.0.2/qemu/target-arm/ |
| H A D | cpu.h | 451 #define CPSR_IT_0_1 (3U << 25) macro
460 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
575 if (mask & CPSR_IT_0_1) { in xpsr_write()
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| H A D | helper.c | 3072 if (mask & CPSR_IT_0_1) { in cpsr_write()
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| /dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/arm/ |
| H A D | cpu.h | 1044 #define CPSR_IT_0_1 (3U << 25) macro
1053 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
1070 #define XPSR_IT_0_1 CPSR_IT_0_1
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| H A D | helper.c | 6119 if (mask & CPSR_IT_0_1) { in cpsr_write()
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| /dports/emulators/qemu-utils/qemu-4.2.1/target/arm/ |
| H A D | cpu.h | 1158 #define CPSR_IT_0_1 (3U << 25) macro
1167 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
1184 #define XPSR_IT_0_1 CPSR_IT_0_1
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| H A D | helper.c | 7506 if (mask & CPSR_IT_0_1) { in cpsr_write()
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| /dports/emulators/qemu42/qemu-4.2.1/target/arm/ |
| H A D | cpu.h | 1158 #define CPSR_IT_0_1 (3U << 25) macro
1167 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
1184 #define XPSR_IT_0_1 CPSR_IT_0_1
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| H A D | helper.c | 7506 if (mask & CPSR_IT_0_1) { in cpsr_write()
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| /dports/emulators/qemu5/qemu-5.2.0/target/arm/ |
| H A D | cpu.h | 1238 #define CPSR_IT_0_1 (3U << 25) macro
1247 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
1262 #define XPSR_IT_0_1 CPSR_IT_0_1
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| H A D | helper.c | 8763 if (mask & CPSR_IT_0_1) { in cpsr_write()
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| /dports/emulators/qemu-guest-agent/qemu-5.0.1/target/arm/ |
| H A D | cpu.h | 1206 #define CPSR_IT_0_1 (3U << 25) macro
1215 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
1230 #define XPSR_IT_0_1 CPSR_IT_0_1
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| H A D | helper.c | 8603 if (mask & CPSR_IT_0_1) { in cpsr_write()
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| /dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/arm/ |
| H A D | cpu.h | 1206 #define CPSR_IT_0_1 (3U << 25) macro
1215 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
1230 #define XPSR_IT_0_1 CPSR_IT_0_1
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| H A D | helper.c | 8602 if (mask & CPSR_IT_0_1) { in cpsr_write()
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| /dports/emulators/qemu60/qemu-6.0.0/target/arm/ |
| H A D | cpu.h | 1256 #define CPSR_IT_0_1 (3U << 25) macro
1265 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
1280 #define XPSR_IT_0_1 CPSR_IT_0_1
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| H A D | helper.c | 8891 if (mask & CPSR_IT_0_1) { in cpsr_write()
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| /dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/arm/ |
| H A D | cpu.h | 1268 #define CPSR_IT_0_1 (3U << 25) macro
1277 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
1292 #define XPSR_IT_0_1 CPSR_IT_0_1
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| H A D | helper.c | 9218 if (mask & CPSR_IT_0_1) { in cpsr_write()
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| /dports/emulators/qemu/qemu-6.2.0/target/arm/ |
| H A D | cpu.h | 1268 #define CPSR_IT_0_1 (3U << 25) macro
1277 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
1292 #define XPSR_IT_0_1 CPSR_IT_0_1
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| H A D | helper.c | 8956 if (mask & CPSR_IT_0_1) { in cpsr_write()
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