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Searched refs:C_PROG_EMPTY_THRESH_ASSERT_VAL (Results 1 – 17 of 17) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/models/
H A DFIFO_GENERATOR_V4_3.v150 parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; constant
321 C_PROG_EMPTY_THRESH_ASSERT_VAL,
402 C_PROG_EMPTY_THRESH_ASSERT_VAL,
486 C_PROG_EMPTY_THRESH_ASSERT_VAL,
722 parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; constant
1858 prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL;
1859 prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_ASSERT_VAL;
1869 prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL;
1965 parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; constant
3116 if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1)
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H A DFIFO_GENERATOR_V6_1.v135 parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, constant
450 C_PROG_EMPTY_THRESH_ASSERT_VAL,
530 C_PROG_EMPTY_THRESH_ASSERT_VAL,
616 C_PROG_EMPTY_THRESH_ASSERT_VAL,
1098 parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, constant
2294 pe_thr_assert_val <= C_PROG_EMPTY_THRESH_ASSERT_VAL - 2;
2297 pe_thr_assert_val <= C_PROG_EMPTY_THRESH_ASSERT_VAL;
2739 parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, constant
4082 if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1)
4091 if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1)
[all …]
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/coregen/
H A Dfifo_xlnx_16x40_2clk.v101 .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
H A Dfifo_xlnx_2Kx36_2clk.v105 .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
H A Dfifo_xlnx_512x36_2clk_18to36.v107 .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
H A Dfifo_xlnx_512x36_2clk_36to18.v103 .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
H A Dfifo_xlnx_64x36_2clk.v105 .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
H A Dfifo_s6_1Kx36_2clk.v107 .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
H A Dfifo_xlnx_512x36_2clk.v105 .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
H A Dfifo_xlnx_512x36_2clk_prog_full.v107 .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
H A Dfifo_s6_512x36_2clk.v107 .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
H A Dfifo_xlnx_16x19_2clk.v105 .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
H A Dfifo_s6_2Kx36_2clk.v107 .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b2xxmini/coregen/
H A Dfifo_short_2clk.v177 .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
H A Dfifo_4k_2clk.v177 .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/coregen/
H A Dfifo_short_2clk.v177 .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
H A Dfifo_4k_2clk.v177 .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),