/dports/devel/avr-libc/avr-libc-2.0.0/include/avr/ |
H A D | iotn24a.h | 645 #define ADC4_DDR DDRA 650 #define USCK_DDR DDRA 655 #define SCL_DDR DDRA 660 #define T1_DDR DDRA 670 #define ADC3_DDR DDRA 675 #define T0_DDR DDRA 685 #define ADC2_DDR DDRA 690 #define AIN1_DDR DDRA 795 #define DI_DDR DDRA 800 #define SDA_DDR DDRA [all …]
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H A D | iotn44a.h | 643 #define ADC4_DDR DDRA 648 #define USCK_DDR DDRA 653 #define SCL_DDR DDRA 658 #define T1_DDR DDRA 668 #define ADC3_DDR DDRA 673 #define T0_DDR DDRA 683 #define ADC2_DDR DDRA 688 #define AIN1_DDR DDRA 793 #define DI_DDR DDRA 798 #define SDA_DDR DDRA [all …]
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H A D | iotn84a.h | 643 #define ADC4_DDR DDRA 648 #define USCK_DDR DDRA 653 #define SCL_DDR DDRA 658 #define T1_DDR DDRA 668 #define ADC3_DDR DDRA 673 #define T0_DDR DDRA 683 #define ADC2_DDR DDRA 688 #define AIN1_DDR DDRA 793 #define DI_DDR DDRA 798 #define SDA_DDR DDRA [all …]
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H A D | iom324pa.h | 64 #define DDRA _SFR_IO8(0x01) macro 1209 #define ADC7_DDR DDRA 1214 #define PCINT7_DDR DDRA 1219 #define ADC6_DDR DDRA 1224 #define PCINT6_DDR DDRA 1229 #define ADC5_DDR DDRA 1239 #define ADC4_DDR DDRA 1249 #define ADC3_DDR DDRA 1259 #define ADC2_DDR DDRA 1269 #define ADC1_DDR DDRA [all …]
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H A D | iom644pa.h | 64 #define DDRA _SFR_IO8(0x01) macro 1224 #define ADC7_DDR DDRA 1229 #define PCINT7_DDR DDRA 1234 #define ADC6_DDR DDRA 1239 #define PCINT6_DDR DDRA 1244 #define ADC5_DDR DDRA 1254 #define ADC4_DDR DDRA 1264 #define ADC3_DDR DDRA 1274 #define ADC2_DDR DDRA 1284 #define ADC1_DDR DDRA [all …]
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H A D | iom16a.h | 313 #define DDRA _SFR_IO8(0x1A) macro 852 #define ADC7_DDR DDRA 857 #define ADC6_DDR DDRA 862 #define ADc5_DDR DDRA 867 #define ADC4_DDR DDRA 872 #define ADC3_DDR DDRA 877 #define ADC2_DDR DDRA 882 #define ADC1_DDR DDRA 887 #define ADC0_DDR DDRA
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H A D | iom169pa.h | 64 #define DDRA _SFR_IO8(0x01) macro 1393 #define SEG3_DDR DDRA 1398 #define SEG2_DDR DDRA 1403 #define SEG1_DDR DDRA 1408 #define SEG0_DDR DDRA 1413 #define COM3_DDR DDRA 1418 #define COM2_DDR DDRA 1423 #define COM1_DDR DDRA 1428 #define COM0_DDR DDRA
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H A D | iom649p.h | 64 #define DDRA _SFR_IO8(0x01) macro 1398 #define SEG3_DDR DDRA 1403 #define SEG2_DDR DDRA 1408 #define SEG1_DDR DDRA 1413 #define SEG0_DDR DDRA 1418 #define COM3_DDR DDRA 1423 #define COM2_DDR DDRA 1428 #define COM1_DDR DDRA 1433 #define COM0_DDR DDRA
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H A D | iom16hva2.h | 58 #define DDRA _SFR_IO8(0x01) macro 827 #define PA0_DDR DDRA 832 #define PA1_DDR DDRA 837 #define PA2_DDR DDRA
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/dports/emulators/lisaem/lisaem-1.2.6.2/lisa/ |
H A D | via6522.c | 950 … via[1].via[ORA]=(via[1].via[IRAA] & (~via[1].via[DDRA])) | (via[1].via[ORAA] & via[1].via[DDRA]); in lisa_wb_Oxdc00_cops_via1() 961 … via[1].via[ORA]=(via[1].via[IRAA] & (~via[1].via[DDRA])) | (via[1].via[ORAA] & via[1].via[DDRA]); in lisa_wb_Oxdc00_cops_via1() 984 via[1].via[DDRA]=xvalue; in lisa_wb_Oxdc00_cops_via1() 1461 … via[2].via[ORA]=(via[2].via[IRAA] & (~via[2].via[DDRA])) | (via[2].via[ORAA] & via[2].via[DDRA]); in lisa_wb_Oxd800_par_via2() 1481 … via[2].via[ORA]=(via[2].via[IRAA] & (~via[2].via[DDRA])) | (via[2].via[ORAA] & via[2].via[DDRA]); in lisa_wb_Oxd800_par_via2() 1517 via[2].via[DDRA],xvalue); in lisa_wb_Oxd800_par_via2() 1519 via[2].via[DDRA]=xvalue; in lisa_wb_Oxd800_par_via2() 2476 V->via[ORA]=(V->via[IRAA] & (~V->via[DDRA])) | (V->via[ORAA] & V->via[DDRA]); in lisa_wb_ext_2par_via() 2496 V->via[ORA]=(V->via[IRAA] & (~V->via[DDRA])) | (V->via[ORAA] & V->via[DDRA]); in lisa_wb_ext_2par_via() 2532 V->via[DDRA],xvalue); in lisa_wb_ext_2par_via() [all …]
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/dports/games/libretro-mame2003/mame2003-libretro-4358db4/src/machine/ |
H A D | 6532riot.c | 17 UINT8 DDRA; member 32 return (r6532[n]->DDRA & r6532[n]->DRA) | (~r6532[n]->DDRA & val); in r6532_combineA() 131 r6532[n]->DDRA = data; in r6532_write() 189 val = r6532[n]->DDRA; in r6532_read() 231 r6532[n]->DDRA = 0; in r6532_init()
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/dports/games/libretro-mame2003_plus/mame2003-plus-libretro-17e9889/src/machine/ |
H A D | 6532riot.c | 17 UINT8 DDRA; member 32 return (r6532[n]->DDRA & r6532[n]->DRA) | (~r6532[n]->DDRA & val); in r6532_combineA() 131 r6532[n]->DDRA = data; in r6532_write() 189 val = r6532[n]->DDRA; in r6532_read() 231 r6532[n]->DDRA = 0; in r6532_init()
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/dports/lang/sdcc/sdcc-4.0.0/device/include/hc08/ |
H A D | mc68hc908jkjl.h | 94 _VOLDATA _UINT8 __at 0x04 DDRA; /* Data Direction Register A */ 95 #define DDRA0 ((struct __hc08_bits *)(&DDRA))->bit0 96 #define DDRA1 ((struct __hc08_bits *)(&DDRA))->bit1 97 #define DDRA2 ((struct __hc08_bits *)(&DDRA))->bit2 98 #define DDRA3 ((struct __hc08_bits *)(&DDRA))->bit3 99 #define DDRA4 ((struct __hc08_bits *)(&DDRA))->bit4 100 #define DDRA5 ((struct __hc08_bits *)(&DDRA))->bit5 101 #define DDRA6 ((struct __hc08_bits *)(&DDRA))->bit6 102 #define DDRA7 ((struct __hc08_bits *)(&DDRA))->bit7
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H A D | mc68hc908qy.h | 77 _VOLDATA _UINT8 __at 0x04 DDRA; /* Data Direction Register A */ 78 #define DDRA0 ((struct __hc08_bits *)(&DDRA))->bit0 79 #define DDRA1 ((struct __hc08_bits *)(&DDRA))->bit1 80 #define DDRA3 ((struct __hc08_bits *)(&DDRA))->bit3 81 #define DDRA4 ((struct __hc08_bits *)(&DDRA))->bit4 82 #define DDRA5 ((struct __hc08_bits *)(&DDRA))->bit5
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H A D | mc68hc908jb8.h | 101 _VOLDATA _UINT8 __at 0x04 DDRA; /* Data Direction Register A */ 102 #define DDRA0 ((struct __hc08_bits *)(&DDRA))->bit0 103 #define DDRA1 ((struct __hc08_bits *)(&DDRA))->bit1 104 #define DDRA2 ((struct __hc08_bits *)(&DDRA))->bit2 105 #define DDRA3 ((struct __hc08_bits *)(&DDRA))->bit3 106 #define DDRA4 ((struct __hc08_bits *)(&DDRA))->bit4 107 #define DDRA5 ((struct __hc08_bits *)(&DDRA))->bit5 108 #define DDRA6 ((struct __hc08_bits *)(&DDRA))->bit6 109 #define DDRA7 ((struct __hc08_bits *)(&DDRA))->bit7
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H A D | mc68hc908gp32.h | 105 _VOLDATA _UINT8 __at 0x04 DDRA; /* Data Direction Register A */ 106 #define DDRA0 ((struct __hc08_bits *)(&DDRA))->bit0 107 #define DDRA1 ((struct __hc08_bits *)(&DDRA))->bit1 108 #define DDRA2 ((struct __hc08_bits *)(&DDRA))->bit2 109 #define DDRA3 ((struct __hc08_bits *)(&DDRA))->bit3 110 #define DDRA4 ((struct __hc08_bits *)(&DDRA))->bit4 111 #define DDRA5 ((struct __hc08_bits *)(&DDRA))->bit5 112 #define DDRA6 ((struct __hc08_bits *)(&DDRA))->bit6 113 #define DDRA7 ((struct __hc08_bits *)(&DDRA))->bit7
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H A D | mc68hc908apxx.h | 105 _VOLDATA _UINT8 __at 0x04 DDRA; /* Data Direction Register A */ 106 #define DDRA0 ((struct __hc08_bits *)(&DDRA))->bit0 107 #define DDRA1 ((struct __hc08_bits *)(&DDRA))->bit1 108 #define DDRA2 ((struct __hc08_bits *)(&DDRA))->bit2 109 #define DDRA3 ((struct __hc08_bits *)(&DDRA))->bit3 110 #define DDRA4 ((struct __hc08_bits *)(&DDRA))->bit4 111 #define DDRA5 ((struct __hc08_bits *)(&DDRA))->bit5 112 #define DDRA6 ((struct __hc08_bits *)(&DDRA))->bit6 113 #define DDRA7 ((struct __hc08_bits *)(&DDRA))->bit7
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/dports/audio/libsidplayfp/libsidplayfp-2.3.1/src/c64/CIA/ |
H A D | mos652x.cpp | 37 DDRA = 2, enumerator 125 ddra(regs[DDRA]), in MOS652X() 193 return (regs[PRA] | ~regs[DDRA]); in read() 233 case DDRA: in write()
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/dports/audio/ocp/ocp-0.2.90/playsid/libsidplayfp-git/src/c64/CIA/ |
H A D | mos6526.cpp | 37 DDRA = 2, enumerator 174 ddra(regs[DDRA]), in MOS6526() 242 return (regs[PRA] | ~regs[DDRA]); in read() 282 case DDRA: in write()
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/dports/emulators/emu64/emu64-5.0.19/src/ |
H A D | mos6522_class.cpp | 43 DDRA = 0xFF; in Reset() 174 DDRA = wert; in WriteIO() 327 return DDRA; in ReadIO()
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/dports/devel/arduino-core/Arduino-b439a77/hardware/arduino/avr/bootloaders/optiboot/ |
H A D | pin_defs.h | 32 #define LED_DDR DDRA 40 #define UART_DDR DDRA
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/dports/devel/arduino-irremote/Arduino-IRremote-3.5.2/src/ |
H A D | digitalWriteFast.h | 176 (((P) >= 22 && (P) <= 29) ? &DDRA : \ 249 … <= 15) ? &DDRD : (((P) >= 16 && (P) <= 23) ? &DDRC : (((P) >= 24 && (P) <= 31) ? &DDRA : &DDRE)))) 263 …(P) <= 7) ? &DDRB : (((P) >= 8 && (P) <= 15) ? &DDRD : (((P) >= 16 && (P) <= 23) ? &DDRC : &DDRA))) 397 #define __digitalPinToDDRReg(P) ((P) <= 7 ? &DDRD : ((P) <= 14 ? &DDRB : ((P) <= 18 ? &DDRA : &DDR… 402 …Reg(P) ((P) <= 7 ? &DDRD : ((P) <= 15 ? &DDRB : ((P) <= 22 ? &DDRC : ((P) <= 26 ? &DDRA : &DDRC)))) 413 #define __digitalPinToDDRReg(P) (((P) <= 4) ? &DDRB : &DDRA) 420 #define __digitalPinToDDRReg(P) (((P) <= 7) ? &DDRA : &DDRB)
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/dports/devel/cc65/cc65-2.19/asminc/ |
H A D | cbm610.inc | 45 DDRA .byte 100 DDRA .byte
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/dports/audio/libsidplay2/sidplay-libs-2.1.1/libsidplay/src/mos6526/ |
H A D | mos6526.cpp | 126 DDRA = 2, enumerator 153 ddra(regs[DDRA]), in MOS6526() 317 case PRA: case DDRA: in write()
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/firmware/octoclock/lib/ |
H A D | init.c | 75 DDRA = 1<<DDA6 | 1<<DDA5 | 1<<DDA4 | 1<<DDA2 | 1<<DDA1 | 1<<DDA0; in setup_atmel_io_ports()
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