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Searched refs:FLASH_CR (Results 1 – 12 of 12) sorted by relevance

/dports/lang/micropython/micropython-1.17/ports/stm32/mboot/
H A Dfwupdate.py99 stm.mem32[stm.FLASH + stm.FLASH_CR] = 1 << 31 # LOCK
106 stm.mem32[stm.FLASH + stm.FLASH_CR] = cr
107 stm.mem32[stm.FLASH + stm.FLASH_CR] = cr | 1 << 16 # STRT
109 stm.mem32[stm.FLASH + stm.FLASH_CR] = 0
116 stm.mem32[stm.FLASH + stm.FLASH_CR] = cr
120 stm.mem32[stm.FLASH + stm.FLASH_CR] = 0
/dports/lang/micropython/micropython-1.17/ports/stm32/boards/NUCLEO_WB55/
H A Drfcore_firmware.py207 if machine.mem32[stm.FLASH + stm.FLASH_CR] & _Flash._FLASH_CR_LOCK_MASK:
215 machine.mem32[stm.FLASH + stm.FLASH_CR] = _Flash._FLASH_CR_LOCK_MASK
221 machine.mem32[stm.FLASH + stm.FLASH_CR] = cr
222 machine.mem32[stm.FLASH + stm.FLASH_CR] = cr | _Flash._FLASH_CR_STRT_MASK
224 machine.mem32[stm.FLASH + stm.FLASH_CR] = 0
230 machine.mem32[stm.FLASH + stm.FLASH_CR] = cr
241 machine.mem32[stm.FLASH + stm.FLASH_CR] = 0
/dports/devel/stlink/stlink-1.7.0/flashloaders/
H A Dstm32f0.s38 # FLASH_CR = 0x01 (set PG)
71 # FLASH_CR &= ~1
H A Dcleanroom.md28 `FLASH_CR`: offset from `flash_base` is 16
37 Before every copy, read a word from FLASH_CR, set the PG bit to 1 and write back. Copy one half wor…
41 Exit: after the copying process and before triggering the breakpoint, clear the PG bit in FLASH_CR.
136 `FLASH_CR`: 相对`flash_base`的offset为16
144 每次拷贝开始前需要读出FLASH_CR处的4字节内容，将其最低bit设置为1，写回FLASH_CR。
150 退出：全部拷贝执行完毕后触发断点前，将FLASH_CR处4字节内容最低bit清为0，写回FLASH_CR。
/dports/devel/openocd/openocd-0.11.0/src/flash/nor/
H A Dstm32h7x.c37 #define FLASH_CR 0x0C macro
312 int retval = stm32x_read_flash_reg(bank, FLASH_CR, &ctrl); in stm32x_unlock_reg()
328 retval = stm32x_read_flash_reg(bank, FLASH_CR, &ctrl); in stm32x_unlock_reg()
373 return stm32x_write_flash_reg(bank, FLASH_CR, FLASH_LOCK); in stm32x_lock_reg()
497 retval = stm32x_write_flash_reg(bank, FLASH_CR, in stm32x_erase()
503 retval = stm32x_write_flash_reg(bank, FLASH_CR, in stm32x_erase()
720 retval = stm32x_write_flash_reg(bank, FLASH_CR, in stm32x_write()
1055 retval = stm32x_write_flash_reg(bank, FLASH_CR, in stm32x_mass_erase()
1060 retval = stm32x_write_flash_reg(bank, FLASH_CR, in stm32x_mass_erase()
H A Dstr9x.c39 #define FLASH_CR 0x54000018 /* Control Register */ macro
640 target_write_u32(target, FLASH_CR, 0x18); in COMMAND_HANDLER()
/dports/sysutils/u-boot-utilite/u-boot-2015.07/board/mpl/pip405/
H A Dpip405.h96 #define FLASH_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + … macro
/dports/devel/thonny/thonny-3.3.14/thonny/plugins/micropython/api_stubs/
H A Dstm.py47 FLASH_CR = 16 variable
/dports/sysutils/u-boot-utilite/u-boot-2015.07/board/mpl/mip405/
H A Dmip405.h131 #define FLASH_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + … macro
H A Dmip405.c280 mtdcr (EBC0_CFGDATA, FLASH_CR); in init_sdram()
/dports/devel/stlink/stlink-1.7.0/src/
H A Dcommon.c48 #define FLASH_CR (FLASH_REGS_ADDR + 0x10) macro
483 reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; in read_flash_cr()
502 cr_reg = FLASH_CR; in is_flash_locked()
603 cr_reg = FLASH_CR; in lock_flash()
606 cr_reg = FLASH_CR; in lock_flash()
659 optcr_reg = FLASH_CR; in is_flash_option_locked()
713 optcr_reg = FLASH_CR; in lock_flash_option()
875 cr_reg = FLASH_CR; in set_flash_cr_pg()
901 cr_reg = FLASH_CR; in clear_flash_cr_pg()
917 cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; in set_flash_cr_per()
[all …]
/dports/devel/openocd/openocd-0.11.0/
H A DChangeLog2430 …ectors - write block size 128 bits (16 bytes) the bit definition of FLASH_CR is different than…
2431 …why we introduced a helper to compute the FLASH_CR value Change-Id: I4da10cde8dd215b1b0f2645f0efdb…