Home
last modified time | relevance | path

Searched refs:INIT_OUT (Results 1 – 4 of 4) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/
H A DWrapBufg.vhd69 -- by using the INIT_OUT attribute.
102 --vhook_a INIT_OUT 0
116 INIT_OUT => 0, --integer:=0
/dports/cad/yosys/yosys-yosys-0.12/techlibs/xilinx/
H A Dcells_sim.v131 parameter [0:0] INIT_OUT = 1'b0; constant
141 wire I0_internal = ((CE0 ^ IS_CE0_INVERTED) ? I0 : INIT_OUT);
142 wire I1_internal = ((CE1 ^ IS_CE1_INVERTED) ? I1 : INIT_OUT);
146 assign O = S0_true ? I0_internal : (S1_true ? I1_internal : INIT_OUT);
157 parameter [0:0] INIT_OUT = 1'b0; constant
161 assign O = ((CE ^ IS_CE_INVERTED) ? I : INIT_OUT);
H A Dcells_xtra.v7492 parameter integer INIT_OUT = 0; constant
/dports/cad/yosys/yosys-yosys-0.12/techlibs/anlogic/
H A Deagle_bb.v39 parameter INIT_OUT = "0"; constant