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Searched refs:MDMA1_D0_IRQ_STATUS (Results 1 – 24 of 24) sorted by relevance

/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/
H A DADSP-EDN-DUAL-CORE-extended_def.h416 #define MDMA1_D0_IRQ_STATUS 0xFFC01F28 macro
H A DADSP-EDN-DUAL-CORE-extended_cdef.h1230 #define pMDMA1_D0_IRQ_STATUS ((uint16_t volatile *)MDMA1_D0_IRQ_STATUS)
1231 #define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS)
1232 #define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS, val)
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/
H A DADSP-EDN-DUAL-CORE-extended_def.h416 #define MDMA1_D0_IRQ_STATUS 0xFFC01F28 macro
H A DADSP-EDN-DUAL-CORE-extended_cdef.h1230 #define pMDMA1_D0_IRQ_STATUS ((uint16_t volatile *)MDMA1_D0_IRQ_STATUS)
1231 #define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS)
1232 #define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS, val)
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/
H A DADSP-EDN-DUAL-CORE-extended_def.h416 #define MDMA1_D0_IRQ_STATUS 0xFFC01F28 macro
H A DADSP-EDN-DUAL-CORE-extended_cdef.h1230 #define pMDMA1_D0_IRQ_STATUS ((uint16_t volatile *)MDMA1_D0_IRQ_STATUS)
1231 #define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS)
1232 #define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS, val)
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/
H A DADSP-EDN-DUAL-CORE-extended_def.h416 #define MDMA1_D0_IRQ_STATUS 0xFFC01F28 macro
H A DADSP-EDN-DUAL-CORE-extended_cdef.h1230 #define pMDMA1_D0_IRQ_STATUS ((uint16_t volatile *)MDMA1_D0_IRQ_STATUS)
1231 #define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS)
1232 #define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS, val)
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/
H A DADSP-EDN-DUAL-CORE-extended_def.h416 #define MDMA1_D0_IRQ_STATUS 0xFFC01F28 macro
H A DADSP-EDN-DUAL-CORE-extended_cdef.h1230 #define pMDMA1_D0_IRQ_STATUS ((uint16_t volatile *)MDMA1_D0_IRQ_STATUS)
1231 #define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS)
1232 #define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS, val)
/dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/
H A DADSP-EDN-DUAL-CORE-extended_def.h416 #define MDMA1_D0_IRQ_STATUS 0xFFC01F28 macro
H A DADSP-EDN-DUAL-CORE-extended_cdef.h1230 #define pMDMA1_D0_IRQ_STATUS ((uint16_t volatile *)MDMA1_D0_IRQ_STATUS)
1231 #define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS)
1232 #define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS, val)
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/
H A DADSP-EDN-DUAL-CORE-extended_def.h416 #define MDMA1_D0_IRQ_STATUS 0xFFC01F28 macro
H A DADSP-EDN-DUAL-CORE-extended_cdef.h1230 #define pMDMA1_D0_IRQ_STATUS ((uint16_t volatile *)MDMA1_D0_IRQ_STATUS)
1231 #define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS)
1232 #define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS, val)
/dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/blackfin/include/asm/mach-bf561/
H A DBF561_def.h418 #define MDMA1_D0_IRQ_STATUS 0xFFC01F28 macro
H A DBF561_cdef.h825 #define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS)
826 #define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS, val)
/dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/blackfin/include/asm/mach-bf538/
H A DBF538_def.h569 #define MDMA1_D0_IRQ_STATUS 0xFFC01F28 macro
H A DBF538_cdef.h1123 #define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS)
1124 #define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS, val)
/dports/devel/arm-none-eabi-newlib/newlib-2.4.0/libgloss/bfin/include/
H A DdefBF561.h528 #define MDMA1_D0_IRQ_STATUS 0xFFC01F28 /*MemDMA1 Stream 0 Destination Interrupt/Status */ macro
H A DcdefBF561.h490 #define pMDMA1_D0_IRQ_STATUS ((volatile unsigned short *)MDMA1_D0_IRQ_STATUS)
H A DcdefBF538.h407 #define pMDMA1_D0_IRQ_STATUS ((volatile unsigned short *)MDMA1_D0_IRQ_STATUS)
H A DdefBF538.h418 #define MDMA1_D0_IRQ_STATUS 0xFFC01F28 /* MemDMA1 Stream 0 Destination Interrupt/Status Register … macro
H A DcdefBF539.h790 #define pMDMA1_D0_IRQ_STATUS ((volatile unsigned short *)MDMA1_D0_IRQ_STATUS)
H A DdefBF539.h656 #define MDMA1_D0_IRQ_STATUS 0xFFC01F28 /* MemDMA1 Stream 0 Destination Interrupt/Status Register … macro