/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/gdb/rdi-share/ |
H A D | tx.c | 33 #define N_MASK 0x3 /* mask for the Encapsulator state */ macro 66 switch ((txstate->tx_state) & N_MASK){ in Angel_TxEngine() 71 txstate->tx_state = (txstate->tx_state & ~N_MASK) | N_BODY; in Angel_TxEngine() 120 txstate->tx_state = (txstate->tx_state & ~N_MASK) | N_ETX; in Angel_TxEngine() 129 txstate->tx_state = (txstate->tx_state & ~N_MASK) | N_IDLE; in Angel_TxEngine() 136 txstate->tx_state = (txstate->tx_state & ~N_MASK) | N_IDLE; in Angel_TxEngine()
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/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/gdb/rdi-share/ |
H A D | tx.c | 33 #define N_MASK 0x3 /* mask for the Encapsulator state */ macro 66 switch ((txstate->tx_state) & N_MASK){ in Angel_TxEngine() 71 txstate->tx_state = (txstate->tx_state & ~N_MASK) | N_BODY; in Angel_TxEngine() 120 txstate->tx_state = (txstate->tx_state & ~N_MASK) | N_ETX; in Angel_TxEngine() 129 txstate->tx_state = (txstate->tx_state & ~N_MASK) | N_IDLE; in Angel_TxEngine() 136 txstate->tx_state = (txstate->tx_state & ~N_MASK) | N_IDLE; in Angel_TxEngine()
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/dports/games/libretro-fbneo/FBNeo-bbe3c05/src/cpu/arm7/ |
H A D | arm7exec.c | 67 SET_CPSR(GET_CPSR & ~(N_MASK | Z_MASK)); 98 SET_CPSR(GET_CPSR & ~(Z_MASK | N_MASK)); 124 SET_CPSR(GET_CPSR & ~(Z_MASK | N_MASK)); 208 SET_CPSR(GET_CPSR & ~(N_MASK | Z_MASK)); 228 SET_CPSR(GET_CPSR & ~(Z_MASK | N_MASK)); 263 SET_CPSR(GET_CPSR & ~(Z_MASK | N_MASK)); 271 SET_CPSR(GET_CPSR & ~(Z_MASK | N_MASK)); 312 SET_CPSR(GET_CPSR & ~(Z_MASK | N_MASK)); 353 SET_CPSR(GET_CPSR & ~(Z_MASK | N_MASK)); 391 SET_CPSR(GET_CPSR & ~(N_MASK | Z_MASK)); [all …]
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H A D | arm7core.c | 237 SET_CPSR(((GET_CPSR & ~(N_MASK | Z_MASK | V_MASK | C_MASK)) \ 244 SET_CPSR(((GET_CPSR & ~(N_MASK | Z_MASK | V_MASK | C_MASK)) \ 255 …SET_CPSR(((GET_CPSR & ~(N_MASK | Z_MASK | V_MASK | C_MASK)) … 262 …SET_CPSR(((GET_CPSR & ~(N_MASK | Z_MASK | V_MASK | C_MASK)) … 282 SET_CPSR(((GET_CPSR & ~(N_MASK | Z_MASK | C_MASK)) \ 1459 SET_CPSR((GET_CPSR & ~(N_MASK | Z_MASK)) | HandleALUNZFlags(r)); in HandleMul() 1497 SET_CPSR((GET_CPSR & ~(N_MASK | Z_MASK)) | HandleLongALUNZFlags(res)); in HandleSMulLong() 1535 SET_CPSR((GET_CPSR & ~(N_MASK | Z_MASK)) | HandleLongALUNZFlags(res)); in HandleUMulLong()
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/dports/games/libretro-fbalpha/fbalpha-84eb9d9/src/cpu/arm7/ |
H A D | arm7exec.c | 66 SET_CPSR(GET_CPSR & ~(N_MASK | Z_MASK)); 97 SET_CPSR(GET_CPSR & ~(Z_MASK | N_MASK)); 123 SET_CPSR(GET_CPSR & ~(Z_MASK | N_MASK)); 207 SET_CPSR(GET_CPSR & ~(N_MASK | Z_MASK)); 227 SET_CPSR(GET_CPSR & ~(Z_MASK | N_MASK)); 262 SET_CPSR(GET_CPSR & ~(Z_MASK | N_MASK)); 270 SET_CPSR(GET_CPSR & ~(Z_MASK | N_MASK)); 311 SET_CPSR(GET_CPSR & ~(Z_MASK | N_MASK)); 352 SET_CPSR(GET_CPSR & ~(Z_MASK | N_MASK)); 390 SET_CPSR(GET_CPSR & ~(N_MASK | Z_MASK)); [all …]
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H A D | arm7core.c | 237 SET_CPSR(((GET_CPSR & ~(N_MASK | Z_MASK | V_MASK | C_MASK)) \ 244 SET_CPSR(((GET_CPSR & ~(N_MASK | Z_MASK | V_MASK | C_MASK)) \ 255 …SET_CPSR(((GET_CPSR & ~(N_MASK | Z_MASK | V_MASK | C_MASK)) … 262 …SET_CPSR(((GET_CPSR & ~(N_MASK | Z_MASK | V_MASK | C_MASK)) … 282 SET_CPSR(((GET_CPSR & ~(N_MASK | Z_MASK | C_MASK)) \ 1459 SET_CPSR((GET_CPSR & ~(N_MASK | Z_MASK)) | HandleALUNZFlags(r)); in HandleMul() 1497 SET_CPSR((GET_CPSR & ~(N_MASK | Z_MASK)) | HandleLongALUNZFlags(res)); in HandleSMulLong() 1535 SET_CPSR((GET_CPSR & ~(N_MASK | Z_MASK)) | HandleLongALUNZFlags(res)); in HandleUMulLong()
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/dports/emulators/mess/mame-mame0226/src/devices/cpu/arm7/ |
H A D | arm7help.h | 26 set_cpsr(((GET_CPSR & ~(N_MASK | Z_MASK | V_MASK | C_MASK)) \ 33 set_cpsr(((GET_CPSR & ~(N_MASK | Z_MASK | V_MASK | C_MASK)) \ 40 UML_AND(block, DRC_CPSR, DRC_CPSR, ~(N_MASK | Z_MASK | V_MASK | C_MASK)); \ 59 …set_cpsr(((GET_CPSR & ~(N_MASK | Z_MASK | V_MASK | C_MASK)) … 66 …set_cpsr(((GET_CPSR & ~(N_MASK | Z_MASK | V_MASK | C_MASK)) … 73 UML_AND(block, DRC_CPSR, DRC_CPSR, ~(N_MASK | Z_MASK | V_MASK | C_MASK)); \ 119 set_cpsr(((GET_CPSR & ~(N_MASK | Z_MASK | C_MASK)) \ 133 UML_AND(block, DRC_CPSR, DRC_CPSR, ~(N_MASK | Z_MASK | C_MASK); \
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H A D | arm7thmb.cpp | 292 set_cpsr(GET_CPSR & ~(N_MASK | Z_MASK)); in tg00_0() 314 set_cpsr(GET_CPSR & ~(Z_MASK | N_MASK)); in tg00_0() 352 set_cpsr(GET_CPSR & ~(Z_MASK | N_MASK)); in tg00_1() 454 set_cpsr(GET_CPSR & ~(Z_MASK | N_MASK)); in tg02_0() 494 set_cpsr(GET_CPSR & ~(Z_MASK | N_MASK)); in tg04_00_00() 504 set_cpsr(GET_CPSR & ~(Z_MASK | N_MASK)); in tg04_00_01() 547 set_cpsr(GET_CPSR & ~(Z_MASK | N_MASK)); in tg04_00_02() 590 set_cpsr(GET_CPSR & ~(Z_MASK | N_MASK)); in tg04_00_03() 630 set_cpsr(GET_CPSR & ~(N_MASK | Z_MASK)); in tg04_00_04() 674 set_cpsr(GET_CPSR & ~(Z_MASK | N_MASK)); in tg04_00_07() [all …]
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H A D | arm7tdrc.hxx | 179 UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK | N_MASK)); in drctg00_0() 211 UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK | N_MASK)); in drctg00_1() 257 UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK | N_MASK)); in drctg01_0() 311 UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK | N_MASK)); in drctg02_0() 357 UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK | N_MASK)); in drctg04_00_00() 1382 UML_TEST(block, DRC_CPSR, N_MASK); in drctg0d_4() 1392 UML_TEST(block, DRC_CPSR, N_MASK); in drctg0d_5() 1456 UML_TEST(block, DRC_CPSR, N_MASK); in drctg0d_a() 1472 UML_TEST(block, DRC_CPSR, N_MASK); in drctg0d_b() 1488 UML_TEST(block, DRC_CPSR, N_MASK); in drctg0d_c() [all …]
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/dports/emulators/mame/mame-mame0226/src/devices/cpu/arm7/ |
H A D | arm7help.h | 26 set_cpsr(((GET_CPSR & ~(N_MASK | Z_MASK | V_MASK | C_MASK)) \ 33 set_cpsr(((GET_CPSR & ~(N_MASK | Z_MASK | V_MASK | C_MASK)) \ 40 UML_AND(block, DRC_CPSR, DRC_CPSR, ~(N_MASK | Z_MASK | V_MASK | C_MASK)); \ 59 …set_cpsr(((GET_CPSR & ~(N_MASK | Z_MASK | V_MASK | C_MASK)) … 66 …set_cpsr(((GET_CPSR & ~(N_MASK | Z_MASK | V_MASK | C_MASK)) … 73 UML_AND(block, DRC_CPSR, DRC_CPSR, ~(N_MASK | Z_MASK | V_MASK | C_MASK)); \ 119 set_cpsr(((GET_CPSR & ~(N_MASK | Z_MASK | C_MASK)) \ 133 UML_AND(block, DRC_CPSR, DRC_CPSR, ~(N_MASK | Z_MASK | C_MASK); \
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H A D | arm7thmb.cpp | 292 set_cpsr(GET_CPSR & ~(N_MASK | Z_MASK)); in tg00_0() 314 set_cpsr(GET_CPSR & ~(Z_MASK | N_MASK)); in tg00_0() 352 set_cpsr(GET_CPSR & ~(Z_MASK | N_MASK)); in tg00_1() 454 set_cpsr(GET_CPSR & ~(Z_MASK | N_MASK)); in tg02_0() 494 set_cpsr(GET_CPSR & ~(Z_MASK | N_MASK)); in tg04_00_00() 504 set_cpsr(GET_CPSR & ~(Z_MASK | N_MASK)); in tg04_00_01() 547 set_cpsr(GET_CPSR & ~(Z_MASK | N_MASK)); in tg04_00_02() 590 set_cpsr(GET_CPSR & ~(Z_MASK | N_MASK)); in tg04_00_03() 630 set_cpsr(GET_CPSR & ~(N_MASK | Z_MASK)); in tg04_00_04() 674 set_cpsr(GET_CPSR & ~(Z_MASK | N_MASK)); in tg04_00_07() [all …]
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/dports/emulators/mess/mame-mame0226/src/devices/cpu/e132xs/ |
H A D | e132xsop.hxx | 83 SR &= ~N_MASK; in hyperstone_movd() 99 SR &= ~(Z_MASK | N_MASK); in hyperstone_movd() 153 SR &= ~(V_MASK | Z_MASK | N_MASK); in hyperstone_divsu() 327 SR |= N_MASK; in hyperstone_cmp() 351 SR &= ~(Z_MASK | N_MASK); in hyperstone_mov() 828 SR |= N_MASK; in hyperstone_cmpi() 854 SR &= ~(Z_MASK | N_MASK); in hyperstone_movi() 2112 SR &= ~(Z_MASK | N_MASK); in hyperstone_mulsu() 2147 …static const uint32_t mask[16] = { 0, 0, 0, 0, (N_MASK | Z_MASK), (N_MASK | Z_MASK), N_MASK, N_MAS… in hyperstone_set() 2170 …static const uint32_t mask[16] = { 0, 0, 0, 0, (N_MASK | Z_MASK), (N_MASK | Z_MASK), N_MASK, N_MAS… in hyperstone_set() [all …]
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H A D | e132xsdrc_ops.hxx | 675 UML_ROLINS(block, I0, I2, 3, N_MASK); in generate_divsu() 1147 UML_ROLINS(block, I6, I2, 3, N_MASK); in generate_add() 1299 UML_ROLINS(block, I5, I1, 3, N_MASK); in generate_subc() 1581 UML_ROLINS(block, I4, I0, 3, N_MASK); in generate_addc() 1646 UML_ROLINS(block, I6, I2, 3, N_MASK); in generate_neg() 2040 UML_OR(block, I3, I3, N_MASK); in generate_cmpi() 2178 UML_ROLINS(block, I6, I3, 3, N_MASK); in generate_addi() 2642 UML_ROLINS(block, I5, I0, 3, N_MASK); in generate_shr() 4287 …static const uint32_t mask[16] = { 0, 0, 0, 0, (N_MASK | Z_MASK), (N_MASK | Z_MASK), N_MASK, N_MAS… in generate_set() 4319 …static const uint32_t mask[16] = { 0, 0, 0, 0, (N_MASK | Z_MASK), (N_MASK | Z_MASK), N_MASK, N_MAS… in generate_set() [all …]
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H A D | 32xsdefs.h | 160 #define N_MASK 0x00000004 macro 181 #define GET_N ((SR & N_MASK)>>2) // bit 2 //NEGATIVE 200 #define SET_N(val) (SR = (SR & ~N_MASK) | ((val) << 2))
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/dports/emulators/mame/mame-mame0226/src/devices/cpu/e132xs/ |
H A D | e132xsop.hxx | 83 SR &= ~N_MASK; in hyperstone_movd() 99 SR &= ~(Z_MASK | N_MASK); in hyperstone_movd() 153 SR &= ~(V_MASK | Z_MASK | N_MASK); in hyperstone_divsu() 327 SR |= N_MASK; in hyperstone_cmp() 351 SR &= ~(Z_MASK | N_MASK); in hyperstone_mov() 828 SR |= N_MASK; in hyperstone_cmpi() 854 SR &= ~(Z_MASK | N_MASK); in hyperstone_movi() 2112 SR &= ~(Z_MASK | N_MASK); in hyperstone_mulsu() 2147 …static const uint32_t mask[16] = { 0, 0, 0, 0, (N_MASK | Z_MASK), (N_MASK | Z_MASK), N_MASK, N_MAS… in hyperstone_set() 2170 …static const uint32_t mask[16] = { 0, 0, 0, 0, (N_MASK | Z_MASK), (N_MASK | Z_MASK), N_MASK, N_MAS… in hyperstone_set() [all …]
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H A D | e132xsdrc_ops.hxx | 675 UML_ROLINS(block, I0, I2, 3, N_MASK); in generate_divsu() 1147 UML_ROLINS(block, I6, I2, 3, N_MASK); in generate_add() 1299 UML_ROLINS(block, I5, I1, 3, N_MASK); in generate_subc() 1581 UML_ROLINS(block, I4, I0, 3, N_MASK); in generate_addc() 1646 UML_ROLINS(block, I6, I2, 3, N_MASK); in generate_neg() 2040 UML_OR(block, I3, I3, N_MASK); in generate_cmpi() 2178 UML_ROLINS(block, I6, I3, 3, N_MASK); in generate_addi() 2642 UML_ROLINS(block, I5, I0, 3, N_MASK); in generate_shr() 4287 …static const uint32_t mask[16] = { 0, 0, 0, 0, (N_MASK | Z_MASK), (N_MASK | Z_MASK), N_MASK, N_MAS… in generate_set() 4319 …static const uint32_t mask[16] = { 0, 0, 0, 0, (N_MASK | Z_MASK), (N_MASK | Z_MASK), N_MASK, N_MAS… in generate_set() [all …]
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H A D | 32xsdefs.h | 160 #define N_MASK 0x00000004 macro 181 #define GET_N ((SR & N_MASK)>>2) // bit 2 //NEGATIVE 200 #define SET_N(val) (SR = (SR & ~N_MASK) | ((val) << 2))
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/dports/audio/gnuspeechsa/gnuspeechsa-0.1.5/src/trm/ |
H A D | SampleRateConverter.cpp | 42 #define N_MASK 0xFFFF0000 macro 47 #define nValue(x) (((x) & N_MASK) >> FRACTION_BITS) 329 timeRegister_ &= (~N_MASK); in dataEmpty() 392 timeRegister_ &= (~N_MASK); in dataEmpty()
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/dports/games/libretro-mame2003/mame2003-libretro-4358db4/src/cpu/arm/ |
H A D | arm.c | 95 #define N_MASK ((data32_t)(1<<N_BIT)) /* Negative flag */ macro 102 #define N_IS_SET(pc) ((pc) & N_MASK) 356 if (!(pc & N_MASK) != !(pc & V_MASK)) goto L_Next; /* Use x ^ (x >> ...) method */ in arm_execute() 359 if (!(pc & N_MASK) == !(pc & V_MASK)) goto L_Next; in arm_execute() 362 if (Z_IS_SET(pc) || (!(pc & N_MASK) != !(pc & V_MASK))) goto L_Next; in arm_execute() 365 if (Z_IS_CLEAR(pc) && (!(pc & N_MASK) == !(pc & V_MASK))) goto L_Next; in arm_execute() 657 (pRegs->sArmRegister[15] & N_MASK) ? 'N' : '-', in arm_info() 883 ((R15 &~ (N_MASK | Z_MASK | V_MASK | C_MASK)) \ 894 ((R15 &~ (N_MASK | Z_MASK | V_MASK | C_MASK)) \ 909 R15 = ((R15 &~ (N_MASK | Z_MASK | C_MASK)) \ [all …]
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/dports/games/libretro-fbneo/FBNeo-bbe3c05/src/cpu/arm/ |
H A D | arm.cpp | 114 #define N_MASK ((UINT32)(1<<N_BIT)) /* Negative flag */ macro 121 #define N_IS_SET(pc) ((pc) & N_MASK) 382 if (!(pc & N_MASK) != !(pc & V_MASK)) goto L_Next; /* Use x ^ (x >> ...) method */ in ArmRun() 385 if (!(pc & N_MASK) == !(pc & V_MASK)) goto L_Next; in ArmRun() 388 if (Z_IS_SET(pc) || (!(pc & N_MASK) != !(pc & V_MASK))) goto L_Next; in ArmRun() 391 if (Z_IS_CLEAR(pc) && (!(pc & N_MASK) == !(pc & V_MASK))) goto L_Next; in ArmRun() 686 ((R15 &~ (N_MASK | Z_MASK | V_MASK | C_MASK)) \ 697 ((R15 &~ (N_MASK | Z_MASK | V_MASK | C_MASK)) \ 712 R15 = ((R15 &~ (N_MASK | Z_MASK | C_MASK)) \ 921 R15 = (R15 &~ (N_MASK | Z_MASK)) | HandleALUNZFlags(r); in HandleMul()
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/dports/games/libretro-fbalpha/fbalpha-84eb9d9/src/cpu/arm/ |
H A D | arm.cpp | 114 #define N_MASK ((UINT32)(1<<N_BIT)) /* Negative flag */ macro 121 #define N_IS_SET(pc) ((pc) & N_MASK) 379 if (!(pc & N_MASK) != !(pc & V_MASK)) goto L_Next; /* Use x ^ (x >> ...) method */ in ArmRun() 382 if (!(pc & N_MASK) == !(pc & V_MASK)) goto L_Next; in ArmRun() 385 if (Z_IS_SET(pc) || (!(pc & N_MASK) != !(pc & V_MASK))) goto L_Next; in ArmRun() 388 if (Z_IS_CLEAR(pc) && (!(pc & N_MASK) == !(pc & V_MASK))) goto L_Next; in ArmRun() 678 ((R15 &~ (N_MASK | Z_MASK | V_MASK | C_MASK)) \ 689 ((R15 &~ (N_MASK | Z_MASK | V_MASK | C_MASK)) \ 704 R15 = ((R15 &~ (N_MASK | Z_MASK | C_MASK)) \ 913 R15 = (R15 &~ (N_MASK | Z_MASK)) | HandleALUNZFlags(r); in HandleMul()
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/dports/emulators/mess/mame-mame0226/src/devices/cpu/arm/ |
H A D | arm.cpp | 96 #define N_MASK ((uint32_t)(1<<N_BIT)) /* Negative flag */ macro 103 #define N_IS_SET(pc) ((pc) & N_MASK) 381 if (!(pc & N_MASK) != !(pc & V_MASK)) goto L_Next; /* Use x ^ (x >> ...) method */ in execute_run() 384 if (!(pc & N_MASK) == !(pc & V_MASK)) goto L_Next; in execute_run() 387 if (Z_IS_SET(pc) || (!(pc & N_MASK) != !(pc & V_MASK))) goto L_Next; in execute_run() 390 if (Z_IS_CLEAR(pc) && (!(pc & N_MASK) == !(pc & V_MASK))) goto L_Next; in execute_run() 558 (m_sArmRegister[15] & N_MASK) ? 'N' : '-', in state_string_export() 765 ((R15 &~ (N_MASK | Z_MASK | V_MASK | C_MASK)) \ 776 ((R15 &~ (N_MASK | Z_MASK | V_MASK | C_MASK)) \ 791 R15 = ((R15 &~ (N_MASK | Z_MASK | C_MASK)) \ [all …]
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/dports/emulators/mame/mame-mame0226/src/devices/cpu/arm/ |
H A D | arm.cpp | 96 #define N_MASK ((uint32_t)(1<<N_BIT)) /* Negative flag */ macro 103 #define N_IS_SET(pc) ((pc) & N_MASK) 381 if (!(pc & N_MASK) != !(pc & V_MASK)) goto L_Next; /* Use x ^ (x >> ...) method */ in execute_run() 384 if (!(pc & N_MASK) == !(pc & V_MASK)) goto L_Next; in execute_run() 387 if (Z_IS_SET(pc) || (!(pc & N_MASK) != !(pc & V_MASK))) goto L_Next; in execute_run() 390 if (Z_IS_CLEAR(pc) && (!(pc & N_MASK) == !(pc & V_MASK))) goto L_Next; in execute_run() 558 (m_sArmRegister[15] & N_MASK) ? 'N' : '-', in state_string_export() 765 ((R15 &~ (N_MASK | Z_MASK | V_MASK | C_MASK)) \ 776 ((R15 &~ (N_MASK | Z_MASK | V_MASK | C_MASK)) \ 791 R15 = ((R15 &~ (N_MASK | Z_MASK | C_MASK)) \ [all …]
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/dports/games/libretro-mame2003_plus/mame2003-plus-libretro-17e9889/src/cpu/arm/ |
H A D | arm.c | 96 #define N_MASK ((data32_t)(1<<N_BIT)) /* Negative flag */ macro 103 #define N_IS_SET(pc) ((pc) & N_MASK) 361 if (!(pc & N_MASK) != !(pc & V_MASK)) goto L_Next; /* Use x ^ (x >> ...) method */ in arm_execute() 364 if (!(pc & N_MASK) == !(pc & V_MASK)) goto L_Next; in arm_execute() 367 if (Z_IS_SET(pc) || (!(pc & N_MASK) != !(pc & V_MASK))) goto L_Next; in arm_execute() 370 if (Z_IS_CLEAR(pc) && (!(pc & N_MASK) == !(pc & V_MASK))) goto L_Next; in arm_execute() 671 (pRegs->sArmRegister[15] & N_MASK) ? 'N' : '-', in arm_info() 902 ((R15 &~ (N_MASK | Z_MASK | V_MASK | C_MASK)) \ 913 ((R15 &~ (N_MASK | Z_MASK | V_MASK | C_MASK)) \ 928 R15 = ((R15 &~ (N_MASK | Z_MASK | C_MASK)) \ [all …]
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/dports/devel/dev86/dev86-0.16.20/ld/ |
H A D | obj.h | 45 #define N_MASK 0x0100 /* entry point */ macro
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