/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 153 SDValue &OffReg, SDValue &ShImm); 1329 OffReg = N.getOperand(1); in SelectT2AddrModeSoReg() 1332 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode()); in SelectT2AddrModeSoReg() 1336 std::swap(Base, OffReg); in SelectT2AddrModeSoReg() 1344 if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt)) in SelectT2AddrModeSoReg() 1345 OffReg = OffReg.getOperand(0); in SelectT2AddrModeSoReg() 1354 if (OffReg.getOpcode() == ISD::MUL && N.hasOneUse()) { in SelectT2AddrModeSoReg() 1357 if (canExtractShiftFromMul(OffReg, 3, PowerOfTwo, NewMulConst)) { in SelectT2AddrModeSoReg() 1358 HandleSDNode Handle(OffReg); in SelectT2AddrModeSoReg() 1359 replaceDAGValue(OffReg.getOperand(1), NewMulConst); in SelectT2AddrModeSoReg() [all …]
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H A D | ARMBaseInstrInfo.cpp | 177 unsigned OffReg = Offset.getReg(); in convertToThreeAddress() local 185 if (OffReg == 0) { in convertToThreeAddress() 202 .addReg(OffReg) in convertToThreeAddress() 211 .addReg(OffReg) in convertToThreeAddress() 219 if (OffReg == 0) in convertToThreeAddress() 231 .addReg(OffReg) in convertToThreeAddress()
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/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 151 SDValue &OffReg, SDValue &ShImm); 1270 OffReg = N.getOperand(1); in SelectT2AddrModeSoReg() 1273 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode()); in SelectT2AddrModeSoReg() 1277 std::swap(Base, OffReg); in SelectT2AddrModeSoReg() 1285 if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt)) in SelectT2AddrModeSoReg() 1286 OffReg = OffReg.getOperand(0); in SelectT2AddrModeSoReg() 1295 if (OffReg.getOpcode() == ISD::MUL && N.hasOneUse()) { in SelectT2AddrModeSoReg() 1298 if (canExtractShiftFromMul(OffReg, 3, PowerOfTwo, NewMulConst)) { in SelectT2AddrModeSoReg() 1299 HandleSDNode Handle(OffReg); in SelectT2AddrModeSoReg() 1300 replaceDAGValue(OffReg.getOperand(1), NewMulConst); in SelectT2AddrModeSoReg() [all …]
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H A D | ARMBaseInstrInfo.cpp | 178 unsigned OffReg = Offset.getReg(); in convertToThreeAddress() local 186 if (OffReg == 0) { in convertToThreeAddress() 203 .addReg(OffReg) in convertToThreeAddress() 212 .addReg(OffReg) in convertToThreeAddress() 220 if (OffReg == 0) in convertToThreeAddress() 232 .addReg(OffReg) in convertToThreeAddress()
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/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 151 SDValue &OffReg, SDValue &ShImm); 1270 OffReg = N.getOperand(1); in SelectT2AddrModeSoReg() 1273 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode()); in SelectT2AddrModeSoReg() 1277 std::swap(Base, OffReg); in SelectT2AddrModeSoReg() 1285 if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt)) in SelectT2AddrModeSoReg() 1286 OffReg = OffReg.getOperand(0); in SelectT2AddrModeSoReg() 1295 if (OffReg.getOpcode() == ISD::MUL && N.hasOneUse()) { in SelectT2AddrModeSoReg() 1298 if (canExtractShiftFromMul(OffReg, 3, PowerOfTwo, NewMulConst)) { in SelectT2AddrModeSoReg() 1299 HandleSDNode Handle(OffReg); in SelectT2AddrModeSoReg() 1300 replaceDAGValue(OffReg.getOperand(1), NewMulConst); in SelectT2AddrModeSoReg() [all …]
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H A D | ARMBaseInstrInfo.cpp | 178 unsigned OffReg = Offset.getReg(); 186 if (OffReg == 0) { 203 .addReg(OffReg) in test_main() 212 .addReg(OffReg) 220 if (OffReg == 0) 232 .addReg(OffReg)
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/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 159 SDValue &OffReg, SDValue &ShImm); 1439 OffReg = N.getOperand(1); in SelectT2AddrModeSoReg() 1442 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode()); in SelectT2AddrModeSoReg() 1446 std::swap(Base, OffReg); in SelectT2AddrModeSoReg() 1454 if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt)) in SelectT2AddrModeSoReg() 1455 OffReg = OffReg.getOperand(0); in SelectT2AddrModeSoReg() 1464 if (OffReg.getOpcode() == ISD::MUL && N.hasOneUse()) { in SelectT2AddrModeSoReg() 1467 if (canExtractShiftFromMul(OffReg, 3, PowerOfTwo, NewMulConst)) { in SelectT2AddrModeSoReg() 1468 HandleSDNode Handle(OffReg); in SelectT2AddrModeSoReg() 1469 replaceDAGValue(OffReg.getOperand(1), NewMulConst); in SelectT2AddrModeSoReg() [all …]
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H A D | ARMBaseInstrInfo.cpp | 177 Register OffReg = Offset.getReg(); in convertToThreeAddress() local 185 if (OffReg == 0) { in convertToThreeAddress() 202 .addReg(OffReg) in convertToThreeAddress() 211 .addReg(OffReg) in convertToThreeAddress() 219 if (OffReg == 0) in convertToThreeAddress() 231 .addReg(OffReg) in convertToThreeAddress()
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 159 SDValue &OffReg, SDValue &ShImm); 1439 OffReg = N.getOperand(1); in SelectT2AddrModeSoReg() 1442 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode()); in SelectT2AddrModeSoReg() 1446 std::swap(Base, OffReg); in SelectT2AddrModeSoReg() 1454 if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt)) in SelectT2AddrModeSoReg() 1455 OffReg = OffReg.getOperand(0); in SelectT2AddrModeSoReg() 1464 if (OffReg.getOpcode() == ISD::MUL && N.hasOneUse()) { in SelectT2AddrModeSoReg() 1467 if (canExtractShiftFromMul(OffReg, 3, PowerOfTwo, NewMulConst)) { in SelectT2AddrModeSoReg() 1468 HandleSDNode Handle(OffReg); in SelectT2AddrModeSoReg() 1469 replaceDAGValue(OffReg.getOperand(1), NewMulConst); in SelectT2AddrModeSoReg() [all …]
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H A D | ARMBaseInstrInfo.cpp | 177 Register OffReg = Offset.getReg(); in convertToThreeAddress() local 185 if (OffReg == 0) { in convertToThreeAddress() 202 .addReg(OffReg) in convertToThreeAddress() 211 .addReg(OffReg) in convertToThreeAddress() 219 if (OffReg == 0) in convertToThreeAddress() 231 .addReg(OffReg) in convertToThreeAddress()
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 159 SDValue &OffReg, SDValue &ShImm); 1439 OffReg = N.getOperand(1); in SelectT2AddrModeSoReg() 1442 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode()); in SelectT2AddrModeSoReg() 1446 std::swap(Base, OffReg); in SelectT2AddrModeSoReg() 1454 if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt)) in SelectT2AddrModeSoReg() 1455 OffReg = OffReg.getOperand(0); in SelectT2AddrModeSoReg() 1464 if (OffReg.getOpcode() == ISD::MUL && N.hasOneUse()) { in SelectT2AddrModeSoReg() 1467 if (canExtractShiftFromMul(OffReg, 3, PowerOfTwo, NewMulConst)) { in SelectT2AddrModeSoReg() 1468 HandleSDNode Handle(OffReg); in SelectT2AddrModeSoReg() 1469 replaceDAGValue(OffReg.getOperand(1), NewMulConst); in SelectT2AddrModeSoReg() [all …]
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H A D | ARMBaseInstrInfo.cpp | 177 Register OffReg = Offset.getReg(); in convertToThreeAddress() local 185 if (OffReg == 0) { in convertToThreeAddress() 202 .addReg(OffReg) in convertToThreeAddress() 211 .addReg(OffReg) in convertToThreeAddress() 219 if (OffReg == 0) in convertToThreeAddress() 231 .addReg(OffReg) in convertToThreeAddress()
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 161 SDValue &OffReg, SDValue &ShImm); 1486 OffReg = N.getOperand(1); in SelectT2AddrModeSoReg() 1489 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode()); in SelectT2AddrModeSoReg() 1493 std::swap(Base, OffReg); in SelectT2AddrModeSoReg() 1501 if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt)) in SelectT2AddrModeSoReg() 1502 OffReg = OffReg.getOperand(0); in SelectT2AddrModeSoReg() 1511 if (OffReg.getOpcode() == ISD::MUL && N.hasOneUse()) { in SelectT2AddrModeSoReg() 1514 if (canExtractShiftFromMul(OffReg, 3, PowerOfTwo, NewMulConst)) { in SelectT2AddrModeSoReg() 1515 HandleSDNode Handle(OffReg); in SelectT2AddrModeSoReg() 1516 replaceDAGValue(OffReg.getOperand(1), NewMulConst); in SelectT2AddrModeSoReg() [all …]
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H A D | ARMBaseInstrInfo.cpp | 186 Register OffReg = Offset.getReg(); in convertToThreeAddress() local 194 if (OffReg == 0) { in convertToThreeAddress() 211 .addReg(OffReg) in convertToThreeAddress() 220 .addReg(OffReg) in convertToThreeAddress() 228 if (OffReg == 0) in convertToThreeAddress() 240 .addReg(OffReg) in convertToThreeAddress()
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 161 SDValue &OffReg, SDValue &ShImm); 1486 OffReg = N.getOperand(1); in SelectT2AddrModeSoReg() 1489 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode()); in SelectT2AddrModeSoReg() 1493 std::swap(Base, OffReg); in SelectT2AddrModeSoReg() 1501 if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt)) in SelectT2AddrModeSoReg() 1502 OffReg = OffReg.getOperand(0); in SelectT2AddrModeSoReg() 1511 if (OffReg.getOpcode() == ISD::MUL && N.hasOneUse()) { in SelectT2AddrModeSoReg() 1514 if (canExtractShiftFromMul(OffReg, 3, PowerOfTwo, NewMulConst)) { in SelectT2AddrModeSoReg() 1515 HandleSDNode Handle(OffReg); in SelectT2AddrModeSoReg() 1516 replaceDAGValue(OffReg.getOperand(1), NewMulConst); in SelectT2AddrModeSoReg() [all …]
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H A D | ARMBaseInstrInfo.cpp | 178 Register OffReg = Offset.getReg(); in convertToThreeAddress() local 186 if (OffReg == 0) { in convertToThreeAddress() 203 .addReg(OffReg) in convertToThreeAddress() 212 .addReg(OffReg) in convertToThreeAddress() 220 if (OffReg == 0) in convertToThreeAddress() 232 .addReg(OffReg) in convertToThreeAddress()
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 161 SDValue &OffReg, SDValue &ShImm); 1486 OffReg = N.getOperand(1); in SelectT2AddrModeSoReg() 1489 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode()); in SelectT2AddrModeSoReg() 1493 std::swap(Base, OffReg); in SelectT2AddrModeSoReg() 1501 if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt)) in SelectT2AddrModeSoReg() 1502 OffReg = OffReg.getOperand(0); in SelectT2AddrModeSoReg() 1511 if (OffReg.getOpcode() == ISD::MUL && N.hasOneUse()) { in SelectT2AddrModeSoReg() 1514 if (canExtractShiftFromMul(OffReg, 3, PowerOfTwo, NewMulConst)) { in SelectT2AddrModeSoReg() 1515 HandleSDNode Handle(OffReg); in SelectT2AddrModeSoReg() 1516 replaceDAGValue(OffReg.getOperand(1), NewMulConst); in SelectT2AddrModeSoReg() [all …]
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/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 161 SDValue &OffReg, SDValue &ShImm); 1486 OffReg = N.getOperand(1); in SelectT2AddrModeSoReg() 1489 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode()); in SelectT2AddrModeSoReg() 1493 std::swap(Base, OffReg); in SelectT2AddrModeSoReg() 1501 if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt)) in SelectT2AddrModeSoReg() 1502 OffReg = OffReg.getOperand(0); in SelectT2AddrModeSoReg() 1511 if (OffReg.getOpcode() == ISD::MUL && N.hasOneUse()) { in SelectT2AddrModeSoReg() 1514 if (canExtractShiftFromMul(OffReg, 3, PowerOfTwo, NewMulConst)) { in SelectT2AddrModeSoReg() 1515 HandleSDNode Handle(OffReg); in SelectT2AddrModeSoReg() 1516 replaceDAGValue(OffReg.getOperand(1), NewMulConst); in SelectT2AddrModeSoReg() [all …]
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 161 SDValue &OffReg, SDValue &ShImm); 1486 OffReg = N.getOperand(1); in SelectT2AddrModeSoReg() 1489 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode()); in SelectT2AddrModeSoReg() 1493 std::swap(Base, OffReg); in SelectT2AddrModeSoReg() 1501 if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt)) in SelectT2AddrModeSoReg() 1502 OffReg = OffReg.getOperand(0); in SelectT2AddrModeSoReg() 1511 if (OffReg.getOpcode() == ISD::MUL && N.hasOneUse()) { in SelectT2AddrModeSoReg() 1514 if (canExtractShiftFromMul(OffReg, 3, PowerOfTwo, NewMulConst)) { in SelectT2AddrModeSoReg() 1515 HandleSDNode Handle(OffReg); in SelectT2AddrModeSoReg() 1516 replaceDAGValue(OffReg.getOperand(1), NewMulConst); in SelectT2AddrModeSoReg() [all …]
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 170 SDValue &OffReg, SDValue &ShImm); 1502 OffReg = N.getOperand(1); in SelectT2AddrModeSoReg() 1505 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode()); in SelectT2AddrModeSoReg() 1509 std::swap(Base, OffReg); in SelectT2AddrModeSoReg() 1517 if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt)) in SelectT2AddrModeSoReg() 1518 OffReg = OffReg.getOperand(0); in SelectT2AddrModeSoReg() 1527 if (OffReg.getOpcode() == ISD::MUL && N.hasOneUse()) { in SelectT2AddrModeSoReg() 1530 if (canExtractShiftFromMul(OffReg, 3, PowerOfTwo, NewMulConst)) { in SelectT2AddrModeSoReg() 1531 HandleSDNode Handle(OffReg); in SelectT2AddrModeSoReg() 1532 replaceDAGValue(OffReg.getOperand(1), NewMulConst); in SelectT2AddrModeSoReg() [all …]
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 170 SDValue &OffReg, SDValue &ShImm); 1502 OffReg = N.getOperand(1); in SelectT2AddrModeSoReg() 1505 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode()); in SelectT2AddrModeSoReg() 1509 std::swap(Base, OffReg); in SelectT2AddrModeSoReg() 1517 if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt)) in SelectT2AddrModeSoReg() 1518 OffReg = OffReg.getOperand(0); in SelectT2AddrModeSoReg() 1527 if (OffReg.getOpcode() == ISD::MUL && N.hasOneUse()) { in SelectT2AddrModeSoReg() 1530 if (canExtractShiftFromMul(OffReg, 3, PowerOfTwo, NewMulConst)) { in SelectT2AddrModeSoReg() 1531 HandleSDNode Handle(OffReg); in SelectT2AddrModeSoReg() 1532 replaceDAGValue(OffReg.getOperand(1), NewMulConst); in SelectT2AddrModeSoReg() [all …]
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 166 SDValue &OffReg, SDValue &ShImm); 1498 OffReg = N.getOperand(1); in SelectT2AddrModeSoReg() 1501 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode()); in SelectT2AddrModeSoReg() 1505 std::swap(Base, OffReg); in SelectT2AddrModeSoReg() 1513 if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt)) in SelectT2AddrModeSoReg() 1514 OffReg = OffReg.getOperand(0); in SelectT2AddrModeSoReg() 1523 if (OffReg.getOpcode() == ISD::MUL && N.hasOneUse()) { in SelectT2AddrModeSoReg() 1526 if (canExtractShiftFromMul(OffReg, 3, PowerOfTwo, NewMulConst)) { in SelectT2AddrModeSoReg() 1527 HandleSDNode Handle(OffReg); in SelectT2AddrModeSoReg() 1528 replaceDAGValue(OffReg.getOperand(1), NewMulConst); in SelectT2AddrModeSoReg() [all …]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 170 SDValue &OffReg, SDValue &ShImm); 1500 OffReg = N.getOperand(1); in SelectT2AddrModeSoReg() 1503 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode()); in SelectT2AddrModeSoReg() 1507 std::swap(Base, OffReg); in SelectT2AddrModeSoReg() 1515 if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt)) in SelectT2AddrModeSoReg() 1516 OffReg = OffReg.getOperand(0); in SelectT2AddrModeSoReg() 1525 if (OffReg.getOpcode() == ISD::MUL && N.hasOneUse()) { in SelectT2AddrModeSoReg() 1528 if (canExtractShiftFromMul(OffReg, 3, PowerOfTwo, NewMulConst)) { in SelectT2AddrModeSoReg() 1529 HandleSDNode Handle(OffReg); in SelectT2AddrModeSoReg() 1530 replaceDAGValue(OffReg.getOperand(1), NewMulConst); in SelectT2AddrModeSoReg() [all …]
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 170 SDValue &OffReg, SDValue &ShImm); 1502 OffReg = N.getOperand(1); in SelectT2AddrModeSoReg() 1505 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode()); in SelectT2AddrModeSoReg() 1509 std::swap(Base, OffReg); in SelectT2AddrModeSoReg() 1517 if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt)) in SelectT2AddrModeSoReg() 1518 OffReg = OffReg.getOperand(0); in SelectT2AddrModeSoReg() 1527 if (OffReg.getOpcode() == ISD::MUL && N.hasOneUse()) { in SelectT2AddrModeSoReg() 1530 if (canExtractShiftFromMul(OffReg, 3, PowerOfTwo, NewMulConst)) { in SelectT2AddrModeSoReg() 1531 HandleSDNode Handle(OffReg); in SelectT2AddrModeSoReg() 1532 replaceDAGValue(OffReg.getOperand(1), NewMulConst); in SelectT2AddrModeSoReg() [all …]
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 170 SDValue &OffReg, SDValue &ShImm); 1502 OffReg = N.getOperand(1); in SelectT2AddrModeSoReg() 1505 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode()); in SelectT2AddrModeSoReg() 1509 std::swap(Base, OffReg); in SelectT2AddrModeSoReg() 1517 if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt)) in SelectT2AddrModeSoReg() 1518 OffReg = OffReg.getOperand(0); in SelectT2AddrModeSoReg() 1527 if (OffReg.getOpcode() == ISD::MUL && N.hasOneUse()) { in SelectT2AddrModeSoReg() 1530 if (canExtractShiftFromMul(OffReg, 3, PowerOfTwo, NewMulConst)) { in SelectT2AddrModeSoReg() 1531 HandleSDNode Handle(OffReg); in SelectT2AddrModeSoReg() 1532 replaceDAGValue(OffReg.getOperand(1), NewMulConst); in SelectT2AddrModeSoReg() [all …]
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