/dports/emulators/qemu42/qemu-4.2.1/roms/skiboot/hw/ |
H A D | npu.c | 175 if (offset != PCI_CFG_CMD) in npu_dev_cfg_write_cmd() 250 PCI_VIRT_CFG_NORMAL_RD(pvd, PCI_CFG_CMD, 4, &pci_cmd); in npu_dev_cfg_bar_write() 1352 PCI_VIRT_CFG_INIT(pvd, PCI_CFG_CMD, 4, 0x00100000, 0xffb802b8, in npu_dev_create_cfg() 1355 pci_virt_add_filter(pvd, PCI_CFG_CMD, 1, PCI_REG_FLAG_WRITE, in npu_dev_create_cfg()
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H A D | phb3.c | 406 pci_cfg_read16(phb, bdfn, PCI_CFG_CMD, &val16); in phb3_root_port_init() 408 pci_cfg_write16(phb, bdfn, PCI_CFG_CMD, val16); in phb3_root_port_init() 471 pci_cfg_read16(phb, bdfn, PCI_CFG_CMD, &val16); in phb3_switch_port_init() 475 pci_cfg_write16(phb, bdfn, PCI_CFG_CMD, val16); in phb3_switch_port_init() 549 pci_cfg_read16(phb, bdfn, PCI_CFG_CMD, &val16); in phb3_endpoint_init() 552 pci_cfg_write16(phb, bdfn, PCI_CFG_CMD, val16); in phb3_endpoint_init() 1719 phb3_pcicfg_read32(&p->phb, 0, PCI_CFG_CMD, &stat->devCmdStatus); in phb3_read_phb_status() 4441 phb3_pcicfg_write16(&p->phb, 0, PCI_CFG_CMD, in phb3_init_hw()
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/dports/emulators/qemu5/qemu-5.2.0/roms/skiboot/hw/ |
H A D | npu.c | 175 if (offset != PCI_CFG_CMD) in npu_dev_cfg_write_cmd() 250 PCI_VIRT_CFG_NORMAL_RD(pvd, PCI_CFG_CMD, 4, &pci_cmd); in npu_dev_cfg_bar_write() 1352 PCI_VIRT_CFG_INIT(pvd, PCI_CFG_CMD, 4, 0x00100000, 0xffb802b8, in npu_dev_create_cfg() 1355 pci_virt_add_filter(pvd, PCI_CFG_CMD, 1, PCI_REG_FLAG_WRITE, in npu_dev_create_cfg()
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H A D | phb3.c | 406 pci_cfg_read16(phb, bdfn, PCI_CFG_CMD, &val16); in phb3_root_port_init() 408 pci_cfg_write16(phb, bdfn, PCI_CFG_CMD, val16); in phb3_root_port_init() 471 pci_cfg_read16(phb, bdfn, PCI_CFG_CMD, &val16); in phb3_switch_port_init() 475 pci_cfg_write16(phb, bdfn, PCI_CFG_CMD, val16); in phb3_switch_port_init() 549 pci_cfg_read16(phb, bdfn, PCI_CFG_CMD, &val16); in phb3_endpoint_init() 552 pci_cfg_write16(phb, bdfn, PCI_CFG_CMD, val16); in phb3_endpoint_init() 1719 phb3_pcicfg_read32(&p->phb, 0, PCI_CFG_CMD, &stat->devCmdStatus); in phb3_read_phb_status() 4441 phb3_pcicfg_write16(&p->phb, 0, PCI_CFG_CMD, in phb3_init_hw()
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/skiboot/hw/ |
H A D | npu.c | 175 if (offset != PCI_CFG_CMD) in npu_dev_cfg_write_cmd() 250 PCI_VIRT_CFG_NORMAL_RD(pvd, PCI_CFG_CMD, 4, &pci_cmd); in npu_dev_cfg_bar_write() 1354 PCI_VIRT_CFG_INIT(pvd, PCI_CFG_CMD, 4, 0x00100000, 0xffb802b8, in npu_dev_create_cfg() 1357 pci_virt_add_filter(pvd, PCI_CFG_CMD, 1, PCI_REG_FLAG_WRITE, in npu_dev_create_cfg()
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H A D | p7ioc-phb.c | 217 p7ioc_pcicfg_read32(&p->phb, 0, PCI_CFG_CMD, &stat->devCmdStatus); in p7ioc_eeh_read_phb_status() 1369 pci_cfg_read16(phb, bdfn, PCI_CFG_CMD, &val16); in p7ioc_root_port_init() 1371 pci_cfg_write16(phb, bdfn, PCI_CFG_CMD, val16); in p7ioc_root_port_init() 1429 pci_cfg_read16(phb, bdfn, PCI_CFG_CMD, &val16); in p7ioc_switch_port_init() 1433 pci_cfg_write16(phb, bdfn, PCI_CFG_CMD, val16); in p7ioc_switch_port_init() 1486 pci_cfg_read16(phb, bdfn, PCI_CFG_CMD, &val16); in p7ioc_endpoint_init() 1489 pci_cfg_write16(phb, bdfn, PCI_CFG_CMD, val16); in p7ioc_endpoint_init() 3144 p7ioc_pcicfg_write16(&p->phb, 0, PCI_CFG_CMD, in p7ioc_phb_init()
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H A D | phb4.c | 423 if ((p->rev == PHB4_REV_NIMBUS_DD10) && (reg == PCI_CFG_CMD)) in phb4_rc_write() 640 pci_cfg_read16(phb, bdfn, PCI_CFG_CMD, &val16); in phb4_root_port_init() 643 pci_cfg_write16(phb, bdfn, PCI_CFG_CMD, val16); in phb4_root_port_init() 704 pci_cfg_read16(phb, bdfn, PCI_CFG_CMD, &val16); in phb4_switch_port_init() 708 pci_cfg_write16(phb, bdfn, PCI_CFG_CMD, val16); in phb4_switch_port_init() 765 pci_cfg_read16(phb, bdfn, PCI_CFG_CMD, &val16); in phb4_endpoint_init() 768 pci_cfg_write16(phb, bdfn, PCI_CFG_CMD, val16); in phb4_endpoint_init() 1832 phb4_pcicfg_read32(&p->phb, 0, PCI_CFG_CMD, &stat->devCmdStatus); in phb4_read_phb_status() 4453 phb4_pcicfg_write16(&p->phb, 0, PCI_CFG_CMD, in phb4_init_hw()
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H A D | npu2.c | 289 if (offset != PCI_CFG_CMD) in npu2_cfg_write_cmd() 379 PCI_VIRT_CFG_NORMAL_RD(pvd, PCI_CFG_CMD, 4, &pci_cmd); in npu2_cfg_write_bar() 1501 PCI_VIRT_CFG_INIT(pvd, PCI_CFG_CMD, 4, 0x00100000, 0xffb802b8, in npu2_populate_cfg() 1504 pci_virt_add_filter(pvd, PCI_CFG_CMD, 1, PCI_REG_FLAG_WRITE, in npu2_populate_cfg()
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H A D | phb3.c | 402 pci_cfg_read16(phb, bdfn, PCI_CFG_CMD, &val16); in phb3_root_port_init() 404 pci_cfg_write16(phb, bdfn, PCI_CFG_CMD, val16); in phb3_root_port_init() 467 pci_cfg_read16(phb, bdfn, PCI_CFG_CMD, &val16); in phb3_switch_port_init() 471 pci_cfg_write16(phb, bdfn, PCI_CFG_CMD, val16); in phb3_switch_port_init() 545 pci_cfg_read16(phb, bdfn, PCI_CFG_CMD, &val16); in phb3_endpoint_init() 548 pci_cfg_write16(phb, bdfn, PCI_CFG_CMD, val16); in phb3_endpoint_init() 1686 phb3_pcicfg_read32(&p->phb, 0, PCI_CFG_CMD, &stat->devCmdStatus); in phb3_read_phb_status() 4326 phb3_pcicfg_write16(&p->phb, 0, PCI_CFG_CMD, in phb3_init_hw()
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/dports/emulators/qemu-utils/qemu-4.2.1/roms/skiboot/hw/ |
H A D | npu.c | 175 if (offset != PCI_CFG_CMD) in npu_dev_cfg_write_cmd() 250 PCI_VIRT_CFG_NORMAL_RD(pvd, PCI_CFG_CMD, 4, &pci_cmd); in npu_dev_cfg_bar_write() 1352 PCI_VIRT_CFG_INIT(pvd, PCI_CFG_CMD, 4, 0x00100000, 0xffb802b8, in npu_dev_create_cfg() 1355 pci_virt_add_filter(pvd, PCI_CFG_CMD, 1, PCI_REG_FLAG_WRITE, in npu_dev_create_cfg()
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H A D | phb3.c | 406 pci_cfg_read16(phb, bdfn, PCI_CFG_CMD, &val16); in phb3_root_port_init() 408 pci_cfg_write16(phb, bdfn, PCI_CFG_CMD, val16); in phb3_root_port_init() 471 pci_cfg_read16(phb, bdfn, PCI_CFG_CMD, &val16); in phb3_switch_port_init() 475 pci_cfg_write16(phb, bdfn, PCI_CFG_CMD, val16); in phb3_switch_port_init() 549 pci_cfg_read16(phb, bdfn, PCI_CFG_CMD, &val16); in phb3_endpoint_init() 552 pci_cfg_write16(phb, bdfn, PCI_CFG_CMD, val16); in phb3_endpoint_init() 1719 phb3_pcicfg_read32(&p->phb, 0, PCI_CFG_CMD, &stat->devCmdStatus); in phb3_read_phb_status() 4441 phb3_pcicfg_write16(&p->phb, 0, PCI_CFG_CMD, in phb3_init_hw()
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/skiboot/hw/ |
H A D | npu.c | 175 if (offset != PCI_CFG_CMD) 250 PCI_VIRT_CFG_NORMAL_RD(pvd, PCI_CFG_CMD, 4, &pci_cmd); 1352 PCI_VIRT_CFG_INIT(pvd, PCI_CFG_CMD, 4, 0x00100000, 0xffb802b8, 1355 pci_virt_add_filter(pvd, PCI_CFG_CMD, 1, PCI_REG_FLAG_WRITE,
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H A D | phb3.c | 406 pci_cfg_read16(phb, bdfn, PCI_CFG_CMD, &val16); in phb3_root_port_init() 408 pci_cfg_write16(phb, bdfn, PCI_CFG_CMD, val16); in phb3_root_port_init() 471 pci_cfg_read16(phb, bdfn, PCI_CFG_CMD, &val16); in phb3_switch_port_init() 475 pci_cfg_write16(phb, bdfn, PCI_CFG_CMD, val16); in phb3_switch_port_init() 549 pci_cfg_read16(phb, bdfn, PCI_CFG_CMD, &val16); in phb3_endpoint_init() 552 pci_cfg_write16(phb, bdfn, PCI_CFG_CMD, val16); in phb3_endpoint_init() 1719 phb3_pcicfg_read32(&p->phb, 0, PCI_CFG_CMD, &stat->devCmdStatus); in phb3_read_phb_status() 4441 phb3_pcicfg_write16(&p->phb, 0, PCI_CFG_CMD, in phb3_init_hw()
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/dports/emulators/qemu/qemu-6.2.0/roms/skiboot/hw/ |
H A D | npu.c | 167 if (offset != PCI_CFG_CMD) in npu_dev_cfg_write_cmd() 242 PCI_VIRT_CFG_NORMAL_RD(pvd, PCI_CFG_CMD, 4, &pci_cmd); in npu_dev_cfg_bar_write() 1346 PCI_VIRT_CFG_INIT(pvd, PCI_CFG_CMD, 4, 0x00100000, 0xffb802b8, in npu_dev_create_cfg() 1349 pci_virt_add_filter(pvd, PCI_CFG_CMD, 1, PCI_REG_FLAG_WRITE, in npu_dev_create_cfg()
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H A D | npu3-nvlink.c | 969 if (offset != PCI_CFG_CMD) in npu3_cfg_cmd() 1314 PCI_VIRT_CFG_INIT(pvd, PCI_CFG_CMD, 4, 0x00100000, 0xffb802b8, in npu3_cfg_populate() 1317 pci_virt_add_filter(pvd, PCI_CFG_CMD, 1, PCI_REG_FLAG_WRITE, in npu3_cfg_populate()
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H A D | phb3.c | 388 pci_cfg_read16(phb, bdfn, PCI_CFG_CMD, &val16); in phb3_root_port_init() 390 pci_cfg_write16(phb, bdfn, PCI_CFG_CMD, val16); in phb3_root_port_init() 453 pci_cfg_read16(phb, bdfn, PCI_CFG_CMD, &val16); in phb3_switch_port_init() 457 pci_cfg_write16(phb, bdfn, PCI_CFG_CMD, val16); in phb3_switch_port_init() 531 pci_cfg_read16(phb, bdfn, PCI_CFG_CMD, &val16); in phb3_endpoint_init() 534 pci_cfg_write16(phb, bdfn, PCI_CFG_CMD, val16); in phb3_endpoint_init() 1701 phb3_pcicfg_read32(&p->phb, 0, PCI_CFG_CMD, &stat->devCmdStatus); in phb3_read_phb_status() 4422 phb3_pcicfg_write16(&p->phb, 0, PCI_CFG_CMD, in phb3_init_hw()
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/dports/emulators/qemu60/qemu-6.0.0/roms/skiboot/hw/ |
H A D | npu.c | 175 if (offset != PCI_CFG_CMD) in npu_dev_cfg_write_cmd() 250 PCI_VIRT_CFG_NORMAL_RD(pvd, PCI_CFG_CMD, 4, &pci_cmd); in npu_dev_cfg_bar_write() 1352 PCI_VIRT_CFG_INIT(pvd, PCI_CFG_CMD, 4, 0x00100000, 0xffb802b8, in npu_dev_create_cfg() 1355 pci_virt_add_filter(pvd, PCI_CFG_CMD, 1, PCI_REG_FLAG_WRITE, in npu_dev_create_cfg()
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/dports/emulators/qemu42/qemu-4.2.1/roms/skiboot/include/ |
H A D | pci-cfg.h | 26 #define PCI_CFG_CMD 0x0004 macro
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/dports/emulators/qemu5/qemu-5.2.0/roms/skiboot/include/ |
H A D | pci-cfg.h | 26 #define PCI_CFG_CMD 0x0004 macro
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/skiboot/include/ |
H A D | pci-cfg.h | 26 #define PCI_CFG_CMD 0x0004 macro
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/dports/emulators/qemu-utils/qemu-4.2.1/roms/skiboot/include/ |
H A D | pci-cfg.h | 26 #define PCI_CFG_CMD 0x0004 macro
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/skiboot/include/ |
H A D | pci-cfg.h | 26 #define PCI_CFG_CMD 0x0004 macro
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/dports/emulators/qemu/qemu-6.2.0/roms/skiboot/include/ |
H A D | pci-cfg.h | 14 #define PCI_CFG_CMD 0x0004 macro
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/dports/emulators/qemu60/qemu-6.0.0/roms/skiboot/include/ |
H A D | pci-cfg.h | 26 #define PCI_CFG_CMD 0x0004 macro
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/dports/devel/arm-none-eabi-newlib/newlib-2.4.0/libgloss/bfin/include/ |
H A D | cdefBF535.h | 435 #define pPCI_CFG_CMD ((volatile unsigned long *)PCI_CFG_CMD)
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