| /dports/emulators/py-unicorn/unicorn-1.0.2/qemu/target-arm/ |
| H A D | cpu.h | 984 #define PL3_R 0x80 macro
986 #define PL2_R (0x20 | PL3_R)
993 #define PL3_RW (PL3_R | PL3_W)
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| H A D | helper.c | 2970 if (r->access & PL3_R) { in define_one_arm_cp_reg_with_opaque()
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| /dports/emulators/unicorn/unicorn-1.0.2/qemu/target-arm/ |
| H A D | cpu.h | 984 #define PL3_R 0x80 macro
986 #define PL2_R (0x20 | PL3_R)
993 #define PL3_RW (PL3_R | PL3_W)
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| H A D | helper.c | 2970 if (r->access & PL3_R) { in define_one_arm_cp_reg_with_opaque()
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| /dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/arm/ |
| H A D | cpu.h | 2033 #define PL3_R 0x80 macro
2035 #define PL2_R (0x20 | PL3_R)
2042 #define PL3_RW (PL3_R | PL3_W)
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| H A D | helper.c | 5298 .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar }, in register_cp_regs_for_features()
5957 if (r->access & PL3_R) { in define_one_arm_cp_reg_with_opaque()
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| /dports/emulators/qemu-utils/qemu-4.2.1/target/arm/ |
| H A D | cpu.h | 2327 #define PL3_R 0x80 macro
2329 #define PL2_R (0x20 | PL3_R)
2348 #define PL3_RW (PL3_R | PL3_W)
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| H A D | helper.c | 6558 .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar }, in register_cp_regs_for_features()
7307 if (r->access & PL3_R) { in define_one_arm_cp_reg_with_opaque()
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| /dports/emulators/qemu42/qemu-4.2.1/target/arm/ |
| H A D | cpu.h | 2327 #define PL3_R 0x80 macro
2329 #define PL2_R (0x20 | PL3_R)
2348 #define PL3_RW (PL3_R | PL3_W)
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| H A D | helper.c | 6558 .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar }, in register_cp_regs_for_features()
7307 if (r->access & PL3_R) { in define_one_arm_cp_reg_with_opaque()
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| /dports/emulators/qemu5/qemu-5.2.0/target/arm/ |
| H A D | cpu.h | 2468 #define PL3_R 0x80 macro
2470 #define PL2_R (0x20 | PL3_R)
2489 #define PL3_RW (PL3_R | PL3_W)
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| H A D | helper.c | 7752 .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar }, in register_cp_regs_for_features()
8564 if (r->access & PL3_R) { in define_one_arm_cp_reg_with_opaque()
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| /dports/emulators/qemu-guest-agent/qemu-5.0.1/target/arm/ |
| H A D | cpu.h | 2414 #define PL3_R 0x80 macro
2416 #define PL2_R (0x20 | PL3_R)
2435 #define PL3_RW (PL3_R | PL3_W)
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| H A D | helper.c | 7634 .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar }, in register_cp_regs_for_features()
8404 if (r->access & PL3_R) { in define_one_arm_cp_reg_with_opaque()
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| /dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/arm/ |
| H A D | cpu.h | 2414 #define PL3_R 0x80 macro
2416 #define PL2_R (0x20 | PL3_R)
2435 #define PL3_RW (PL3_R | PL3_W)
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| H A D | helper.c | 7633 .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar }, in register_cp_regs_for_features()
8403 if (r->access & PL3_R) { in define_one_arm_cp_reg_with_opaque()
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| /dports/emulators/qemu60/qemu-6.0.0/target/arm/ |
| H A D | cpu.h | 2617 #define PL3_R 0x80 macro
2619 #define PL2_R (0x20 | PL3_R)
2638 #define PL3_RW (PL3_R | PL3_W)
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| H A D | helper.c | 7878 .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar }, in register_cp_regs_for_features()
8693 if (r->access & PL3_R) { in define_one_arm_cp_reg_with_opaque()
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| /dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/arm/ |
| H A D | cpu.h | 2654 #define PL3_R 0x80 macro
2656 #define PL2_R (0x20 | PL3_R)
2675 #define PL3_RW (PL3_R | PL3_W)
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| H A D | helper.c | 8197 .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar }, in register_cp_regs_for_features()
9018 if (r->access & PL3_R) { in define_one_arm_cp_reg_with_opaque()
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| /dports/emulators/qemu/qemu-6.2.0/target/arm/ |
| H A D | cpu.h | 2654 #define PL3_R 0x80 macro
2656 #define PL2_R (0x20 | PL3_R)
2675 #define PL3_RW (PL3_R | PL3_W)
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| H A D | helper.c | 7973 .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar }, in register_cp_regs_for_features()
8756 if (r->access & PL3_R) { in define_one_arm_cp_reg_with_opaque()
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