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Searched refs:Std_Logic_Vector (Results 1 – 11 of 11) sorted by relevance

/dports/cad/alliance/alliance/src/documentation/alliance-examples/multi8b/
H A Dmulti8.vhdl7 port ( X : in Std_Logic_Vector(7 downto 0) ;
8 Y : in Std_Logic_Vector(7 downto 0) ;
17 signal PP1 : Std_Logic_Vector(8 downto 0);
18 signal PP2 : Std_Logic_Vector(8 downto 0);
19 signal PP3 : Std_Logic_Vector(8 downto 0);
20 signal PP4 : Std_Logic_Vector(8 downto 0);
21 signal PP5 : Std_Logic_Vector(8 downto 0);
22 signal PP6 : Std_Logic_Vector(8 downto 0);
23 signal PP7 : Std_Logic_Vector(8 downto 0);
24 signal PP8 : Std_Logic_Vector(8 downto 0);
[all …]
/dports/cad/alliance/alliance/src/documentation/alliance-examples/multi4b/
H A Dmulti4.vhdl7 port ( X : in Std_Logic_Vector(3 downto 0) ;
8 Y : in Std_Logic_Vector(3 downto 0) ;
9 R : out Std_Logic_Vector(7 downto 0) );
17 signal PP1 : Std_Logic_Vector(4 downto 0);
18 signal PP2 : Std_Logic_Vector(4 downto 0);
19 signal PP3 : Std_Logic_Vector(4 downto 0);
20 signal PP4 : Std_Logic_Vector(4 downto 0);
22 signal PP12 : Std_Logic_Vector(5 downto 0);
23 signal PP34 : Std_Logic_Vector(5 downto 0);
/dports/cad/alliance/alliance/src/documentation/alliance-examples/multi16b-reg/
H A Dmulti16.vhdl8 X : in Std_Logic_Vector(15 downto 0) ;
9 Y : in Std_Logic_Vector(15 downto 0) ;
18 signal PP1 : Std_Logic_Vector(16 downto 0);
19 signal PP2 : Std_Logic_Vector(16 downto 0);
20 signal PP3 : Std_Logic_Vector(16 downto 0);
21 signal PP4 : Std_Logic_Vector(16 downto 0);
22 signal PP5 : Std_Logic_Vector(16 downto 0);
23 signal PP6 : Std_Logic_Vector(16 downto 0);
24 signal PP7 : Std_Logic_Vector(16 downto 0);
25 signal PP8 : Std_Logic_Vector(16 downto 0);
[all …]
/dports/cad/alliance/alliance/src/documentation/alliance-examples/multi8/
H A Dmulti8.vhdl10 port ( A : in Std_Logic_Vector(7 downto 0) ;
11 B : in Std_Logic_Vector(7 downto 0) ;
16 RESULT : out Std_Logic_Vector(15 downto 0) ;
41 B : in Std_Logic_Vector(7 downto 0) ;
43 OUTS : out Std_Logic_Vector(15 downto 0) );
49 OUTS : in Std_Logic_Vector(15 downto 0) ;
52 RESULT : out Std_Logic_Vector(15 downto 0) );
60 A : in Std_Logic_Vector(7 downto 0) ;
H A Daddaccu.vhdl11 OUTS : in Std_Logic_Vector(15 downto 0) ;
14 RESULT : out Std_Logic_Vector(15 downto 0) );
22 signal resultint : Std_Logic_Vector(15 downto 0) ;
H A Dsrb.vhdl11 B : in Std_Logic_Vector(7 downto 0);
13 OUTS : out Std_Logic_Vector(15 downto 0));
21 signal outsint : Std_Logic_Vector(15 downto 0);
H A Dsra.vhdl12 A : in Std_Logic_Vector(7 downto 0);
24 signal outsint : Std_Logic_Vector(7 downto 0);
/dports/cad/alliance/alliance/src/documentation/alliance-examples/adder4/
H A Dadder4.vhdl9 port ( A : in Std_Logic_Vector(3 downto 0) ;
10 B : in Std_Logic_Vector(3 downto 0) ;
11 RESULT : out Std_Logic_Vector(3 downto 0) );
/dports/cad/alliance/alliance/src/documentation/alliance-examples/addaccu16/
H A Daddaccu.vhdl12 A : in Std_Logic_Vector(15 downto 0) ;
13 RESULT : out Std_Logic_Vector(15 downto 0) );
19 signal resultint : Std_Logic_Vector(15 downto 0) ;
/dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/ticket29/
H A Ddebugtools.vhdl8 function to_string(sv: Std_Logic_Vector) return string;
9 function to_hstring(sv: Std_Logic_Vector) return string;
56 function to_string(sv: Std_Logic_Vector) return string is
66 function to_hstring(sv: Std_Logic_Vector) return string is
/dports/cad/ghdl/ghdl-1.0.0/pyGHDL/libghdl/
H A Dstd_names.py590 Std_Logic_Vector = 795 variable in Name