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Searched refs:bneg (Results 1 – 25 of 514) sorted by relevance

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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/Thumb2/
H A Dcsel.ll193 %bneg = sub i32 0, %b
194 %spec.select = select i1 %cmp, i32 %bneg, i32 %c
206 %bneg = sub i32 0, %b
219 %bneg = sub i32 0, %b
232 %bneg = sub i32 0, %b
245 %bneg = sub i32 0, %b
258 %bneg = sub i32 0, %b
271 %bneg = sub i32 0, %b
284 %bneg = sub i32 0, %b
297 %bneg = sub i32 0, %b
[all …]
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/Thumb2/
H A Dcsel.ll193 %bneg = sub i32 0, %b
194 %spec.select = select i1 %cmp, i32 %bneg, i32 %c
206 %bneg = sub i32 0, %b
219 %bneg = sub i32 0, %b
232 %bneg = sub i32 0, %b
245 %bneg = sub i32 0, %b
258 %bneg = sub i32 0, %b
271 %bneg = sub i32 0, %b
284 %bneg = sub i32 0, %b
297 %bneg = sub i32 0, %b
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/Thumb2/
H A Dcsel.ll191 %bneg = sub i32 0, %b
192 %spec.select = select i1 %cmp, i32 %bneg, i32 %c
204 %bneg = sub i32 0, %b
217 %bneg = sub i32 0, %b
230 %bneg = sub i32 0, %b
243 %bneg = sub i32 0, %b
256 %bneg = sub i32 0, %b
269 %bneg = sub i32 0, %b
282 %bneg = sub i32 0, %b
295 %bneg = sub i32 0, %b
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/Thumb2/
H A Dcsel.ll191 %bneg = sub i32 0, %b
192 %spec.select = select i1 %cmp, i32 %bneg, i32 %c
204 %bneg = sub i32 0, %b
217 %bneg = sub i32 0, %b
230 %bneg = sub i32 0, %b
243 %bneg = sub i32 0, %b
256 %bneg = sub i32 0, %b
269 %bneg = sub i32 0, %b
282 %bneg = sub i32 0, %b
295 %bneg = sub i32 0, %b
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/Thumb2/
H A Dcsel.ll191 %bneg = sub i32 0, %b
192 %spec.select = select i1 %cmp, i32 %bneg, i32 %c
204 %bneg = sub i32 0, %b
217 %bneg = sub i32 0, %b
230 %bneg = sub i32 0, %b
243 %bneg = sub i32 0, %b
256 %bneg = sub i32 0, %b
269 %bneg = sub i32 0, %b
282 %bneg = sub i32 0, %b
295 %bneg = sub i32 0, %b
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/Thumb2/
H A Dcsel.ll193 %bneg = sub i32 0, %b
194 %spec.select = select i1 %cmp, i32 %bneg, i32 %c
206 %bneg = sub i32 0, %b
219 %bneg = sub i32 0, %b
232 %bneg = sub i32 0, %b
245 %bneg = sub i32 0, %b
258 %bneg = sub i32 0, %b
271 %bneg = sub i32 0, %b
284 %bneg = sub i32 0, %b
297 %bneg = sub i32 0, %b
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/Thumb2/
H A Dcsel.ll191 %bneg = sub i32 0, %b
192 %spec.select = select i1 %cmp, i32 %bneg, i32 %c
204 %bneg = sub i32 0, %b
217 %bneg = sub i32 0, %b
230 %bneg = sub i32 0, %b
243 %bneg = sub i32 0, %b
256 %bneg = sub i32 0, %b
269 %bneg = sub i32 0, %b
282 %bneg = sub i32 0, %b
295 %bneg = sub i32 0, %b
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/Thumb2/
H A Dcsel.ll191 %bneg = sub i32 0, %b
192 %spec.select = select i1 %cmp, i32 %bneg, i32 %c
204 %bneg = sub i32 0, %b
217 %bneg = sub i32 0, %b
230 %bneg = sub i32 0, %b
243 %bneg = sub i32 0, %b
256 %bneg = sub i32 0, %b
269 %bneg = sub i32 0, %b
282 %bneg = sub i32 0, %b
295 %bneg = sub i32 0, %b
[all …]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/Thumb2/
H A Dcsel.ll193 %bneg = sub i32 0, %b
194 %spec.select = select i1 %cmp, i32 %bneg, i32 %c
206 %bneg = sub i32 0, %b
219 %bneg = sub i32 0, %b
232 %bneg = sub i32 0, %b
245 %bneg = sub i32 0, %b
258 %bneg = sub i32 0, %b
271 %bneg = sub i32 0, %b
284 %bneg = sub i32 0, %b
297 %bneg = sub i32 0, %b
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/Thumb2/
H A Dcsel.ll191 %bneg = sub i32 0, %b
192 %spec.select = select i1 %cmp, i32 %bneg, i32 %c
204 %bneg = sub i32 0, %b
217 %bneg = sub i32 0, %b
230 %bneg = sub i32 0, %b
243 %bneg = sub i32 0, %b
256 %bneg = sub i32 0, %b
269 %bneg = sub i32 0, %b
282 %bneg = sub i32 0, %b
295 %bneg = sub i32 0, %b
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/Thumb2/
H A Dcsel.ll191 %bneg = sub i32 0, %b
192 %spec.select = select i1 %cmp, i32 %bneg, i32 %c
204 %bneg = sub i32 0, %b
217 %bneg = sub i32 0, %b
230 %bneg = sub i32 0, %b
243 %bneg = sub i32 0, %b
256 %bneg = sub i32 0, %b
269 %bneg = sub i32 0, %b
282 %bneg = sub i32 0, %b
295 %bneg = sub i32 0, %b
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/Thumb2/
H A Dcsel.ll191 %bneg = sub i32 0, %b
192 %spec.select = select i1 %cmp, i32 %bneg, i32 %c
204 %bneg = sub i32 0, %b
217 %bneg = sub i32 0, %b
230 %bneg = sub i32 0, %b
243 %bneg = sub i32 0, %b
256 %bneg = sub i32 0, %b
269 %bneg = sub i32 0, %b
282 %bneg = sub i32 0, %b
295 %bneg = sub i32 0, %b
[all …]
/dports/security/p5-Crypt-Perl/Crypt-Perl-0.34/lib/Crypt/Perl/ECDSA/EC/
H A DPoint.pm128 …my $x3 = $w->copy()->bmuladd( $w, $y1sqz1->copy()->bmul($x1)->blsft($bi3)->bneg() )->bmul($bi2)->b…
143 $w->copy()->bmul($bi3)->bmuladd($x1, $y1sqz1->blsft($bi1)->bneg()),
146 $w->bpow($bi3)->bneg(),
233 $self->{'y'}->to_bigint()->copy()->bneg()->bmul($b->{'z'}),
241 $self->{'x'}->to_bigint()->copy()->bneg()->bmul($b->{'z'}),
289 $x3->bmuladd( $z1, $x1->copy()->blsft($bi1)->bneg()->bmul($v)->bmul($v) );
290 $x3->bmuladd( $z2, $v->copy()->bpow($bi3)->bneg() );
297 $y3->bmuladd($v2, $y1->copy()->bmul($v3)->bneg()); #no more y1 after this
/dports/math/p5-Math-BigInt/Math-BigInt-1.999827/t/
H A Dalias.inc16 $x->bneg();
17 is($x->is_pos(), 0, "$CLASS -> new(123) -> bneg() -> is_pos()");
18 is($x->is_neg(), 1, "$CLASS -> new(123) -> bneg() -> is_neg()");
/dports/math/p5-Math-ProvablePrime/Math-ProvablePrime-0.045/lib/Math/
H A DProvablePrime.pm612 return $bigint->copy()->bsqrt()->bneg()->btdiv(1)->bneg();
699 $bb->bmul($bb)->bneg()->btdiv($_MBI_200)->bneg();
/dports/lang/perl5.30/perl-5.30.3/cpan/Math-BigInt/t/Math/BigInt/
H A DSubclass.pm60 *bneg = \&Math::BigInt::bneg;
/dports/lang/perl5.32/perl-5.32.1/cpan/Math-BigInt/t/Math/BigInt/
H A DSubclass.pm60 *bneg = \&Math::BigInt::bneg;
/dports/lang/perl5.34/perl-5.34.0/cpan/Math-BigInt/t/Math/BigInt/
H A DSubclass.pm60 *bneg = \&Math::BigInt::bneg;
/dports/math/p5-Math-BigInt/Math-BigInt-1.999827/t/Math/BigInt/
H A DSubclass.pm60 *bneg = \&Math::BigInt::bneg;
/dports/lang/perl5-devel/perl5-5.35.4-102-ge43d289c7c/cpan/Math-BigInt/t/Math/BigInt/
H A DSubclass.pm60 *bneg = \&Math::BigInt::bneg;
/dports/math/cgal/CGAL-5.3/include/CGAL/Min_sphere_of_spheres_d/
H A DMin_sphere_of_spheres_d_pair.h200 const bool aneg = p.first<FT(0), bneg = p.second<FT(0);
202 if (aneg && bneg)
204 if (!aneg && !bneg)
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/Mips/msa/
H A Dshift_no_and.ll90 %2 = tail call <16 x i8> @llvm.mips.bneg.b(<16 x i8> %0, <16 x i8> %1)
95 declare <16 x i8> @llvm.mips.bneg.b(<16 x i8>, <16 x i8>) nounwind
99 ; CHECK: bneg.b
109 %2 = tail call <8 x i16> @llvm.mips.bneg.h(<8 x i16> %0, <8 x i16> %1)
114 declare <8 x i16> @llvm.mips.bneg.h(<8 x i16>, <8 x i16>) nounwind
118 ; CHECK: bneg.h
128 %2 = tail call <4 x i32> @llvm.mips.bneg.w(<4 x i32> %0, <4 x i32> %1)
133 declare <4 x i32> @llvm.mips.bneg.w(<4 x i32>, <4 x i32>) nounwind
137 ; CHECK: bneg.w
152 declare <2 x i64> @llvm.mips.bneg.d(<2 x i64>, <2 x i64>) nounwind
[all …]
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/Mips/msa/
H A Dshift_no_and.ll90 %2 = tail call <16 x i8> @llvm.mips.bneg.b(<16 x i8> %0, <16 x i8> %1)
95 declare <16 x i8> @llvm.mips.bneg.b(<16 x i8>, <16 x i8>) nounwind
99 ; CHECK: bneg.b
109 %2 = tail call <8 x i16> @llvm.mips.bneg.h(<8 x i16> %0, <8 x i16> %1)
114 declare <8 x i16> @llvm.mips.bneg.h(<8 x i16>, <8 x i16>) nounwind
118 ; CHECK: bneg.h
128 %2 = tail call <4 x i32> @llvm.mips.bneg.w(<4 x i32> %0, <4 x i32> %1)
133 declare <4 x i32> @llvm.mips.bneg.w(<4 x i32>, <4 x i32>) nounwind
137 ; CHECK: bneg.w
152 declare <2 x i64> @llvm.mips.bneg.d(<2 x i64>, <2 x i64>) nounwind
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/Mips/msa/
H A Dshift_no_and.ll90 %2 = tail call <16 x i8> @llvm.mips.bneg.b(<16 x i8> %0, <16 x i8> %1)
95 declare <16 x i8> @llvm.mips.bneg.b(<16 x i8>, <16 x i8>) nounwind
99 ; CHECK: bneg.b
109 %2 = tail call <8 x i16> @llvm.mips.bneg.h(<8 x i16> %0, <8 x i16> %1)
114 declare <8 x i16> @llvm.mips.bneg.h(<8 x i16>, <8 x i16>) nounwind
118 ; CHECK: bneg.h
128 %2 = tail call <4 x i32> @llvm.mips.bneg.w(<4 x i32> %0, <4 x i32> %1)
133 declare <4 x i32> @llvm.mips.bneg.w(<4 x i32>, <4 x i32>) nounwind
137 ; CHECK: bneg.w
152 declare <2 x i64> @llvm.mips.bneg.d(<2 x i64>, <2 x i64>) nounwind
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/Mips/msa/
H A Dshift_no_and.ll90 %2 = tail call <16 x i8> @llvm.mips.bneg.b(<16 x i8> %0, <16 x i8> %1)
95 declare <16 x i8> @llvm.mips.bneg.b(<16 x i8>, <16 x i8>) nounwind
99 ; CHECK: bneg.b
109 %2 = tail call <8 x i16> @llvm.mips.bneg.h(<8 x i16> %0, <8 x i16> %1)
114 declare <8 x i16> @llvm.mips.bneg.h(<8 x i16>, <8 x i16>) nounwind
118 ; CHECK: bneg.h
128 %2 = tail call <4 x i32> @llvm.mips.bneg.w(<4 x i32> %0, <4 x i32> %1)
133 declare <4 x i32> @llvm.mips.bneg.w(<4 x i32>, <4 x i32>) nounwind
137 ; CHECK: bneg.w
152 declare <2 x i64> @llvm.mips.bneg.d(<2 x i64>, <2 x i64>) nounwind
[all …]

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