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Searched refs:condexec_bits (Results 1 – 25 of 50) sorted by relevance

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/dports/emulators/x49gp/x49gp/x49gp-code/qemu/qemu-git/target-arm/
H A Dcpu.h99 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ member
272 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) in xpsr_read()
273 | ((env->condexec_bits & 0xfc) << 8) in xpsr_read()
291 env->condexec_bits &= ~3; in xpsr_write()
292 env->condexec_bits |= (val >> 25) & 3; in xpsr_write()
295 env->condexec_bits &= 3; in xpsr_write()
296 env->condexec_bits |= (val >> 8) & 0xfc; in xpsr_write()
450 | (env->vfp.vec_stride << 4) | (env->condexec_bits << 8); in cpu_get_tb_cpu_state()
H A Dhelper.c372 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) in cpsr_read()
373 | ((env->condexec_bits & 0xfc) << 8) in cpsr_read()
390 env->condexec_bits &= ~3; in cpsr_write()
391 env->condexec_bits |= (val >> 25) & 3; in cpsr_write()
394 env->condexec_bits &= 3; in cpsr_write()
395 env->condexec_bits |= (val >> 8) & 0xfc; in cpsr_write()
827 env->condexec_bits = 0; in do_interrupt()
/dports/emulators/py-unicorn/unicorn-1.0.2/qemu/target-arm/
H A Dcpu.h171 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ member
557 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) in xpsr_read()
558 | ((env->condexec_bits & 0xfc) << 8) in xpsr_read()
576 env->condexec_bits &= ~3; in xpsr_write()
577 env->condexec_bits |= (val >> 25) & 3; in xpsr_write()
580 env->condexec_bits &= 3; in xpsr_write()
581 env->condexec_bits |= (val >> 8) & 0xfc; in xpsr_write()
1494 | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT) in cpu_get_tb_cpu_state()
H A Dhelper-a64.c518 env->condexec_bits = 0; in aarch64_cpu_do_interrupt()
H A Dhelper.c3055 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) in cpsr_read()
3056 | ((env->condexec_bits & 0xfc) << 8) in cpsr_read()
3073 env->condexec_bits &= ~3; in cpsr_write()
3074 env->condexec_bits |= (val >> 25) & 3; in cpsr_write()
3077 env->condexec_bits &= 3; in cpsr_write()
3078 env->condexec_bits |= (val >> 8) & 0xfc; in cpsr_write()
3462 env->condexec_bits = 0; in arm_v7m_cpu_do_interrupt()
3643 env->condexec_bits = 0; in arm_cpu_do_interrupt()
/dports/emulators/unicorn/unicorn-1.0.2/qemu/target-arm/
H A Dcpu.h171 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ member
557 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) in xpsr_read()
558 | ((env->condexec_bits & 0xfc) << 8) in xpsr_read()
576 env->condexec_bits &= ~3; in xpsr_write()
577 env->condexec_bits |= (val >> 25) & 3; in xpsr_write()
580 env->condexec_bits &= 3; in xpsr_write()
581 env->condexec_bits |= (val >> 8) & 0xfc; in xpsr_write()
1494 | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT) in cpu_get_tb_cpu_state()
H A Dhelper-a64.c518 env->condexec_bits = 0; in aarch64_cpu_do_interrupt()
H A Dhelper.c3055 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) in cpsr_read()
3056 | ((env->condexec_bits & 0xfc) << 8) in cpsr_read()
3073 env->condexec_bits &= ~3; in cpsr_write()
3074 env->condexec_bits |= (val >> 25) & 3; in cpsr_write()
3077 env->condexec_bits &= 3; in cpsr_write()
3078 env->condexec_bits |= (val >> 8) & 0xfc; in cpsr_write()
3462 env->condexec_bits = 0; in arm_v7m_cpu_do_interrupt()
3643 env->condexec_bits = 0; in arm_cpu_do_interrupt()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/arm/
H A Dcpu.h260 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ member
1180 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) in xpsr_read()
1181 | ((env->condexec_bits & 0xfc) << 8) in xpsr_read()
1201 env->condexec_bits &= ~3; in xpsr_write()
1202 env->condexec_bits |= (val >> 25) & 3; in xpsr_write()
1205 env->condexec_bits &= 3; in xpsr_write()
1206 env->condexec_bits |= (val >> 8) & 0xfc; in xpsr_write()
H A Dhelper.c6099 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) in cpsr_read()
6100 | ((env->condexec_bits & 0xfc) << 8) in cpsr_read()
6120 env->condexec_bits &= ~3; in cpsr_write()
6121 env->condexec_bits |= (val >> 25) & 3; in cpsr_write()
6124 env->condexec_bits &= 3; in cpsr_write()
6125 env->condexec_bits |= (val >> 8) & 0xfc; in cpsr_write()
7058 env->condexec_bits = 0; in v7m_exception_taken()
8114 env->condexec_bits = 0; in take_aarch32_exception()
8458 env->condexec_bits = 0; in arm_cpu_do_interrupt_aarch64()
12700 | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT) in cpu_get_tb_cpu_state()
/dports/emulators/qemu-utils/qemu-4.2.1/target/arm/
H A Dcpu.h262 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ member
1296 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) in xpsr_read()
1297 | ((env->condexec_bits & 0xfc) << 8) in xpsr_read()
1322 env->condexec_bits &= ~3; in xpsr_write()
1323 env->condexec_bits |= (val >> 25) & 3; in xpsr_write()
1326 env->condexec_bits &= 3; in xpsr_write()
1327 env->condexec_bits |= (val >> 8) & 0xfc; in xpsr_write()
H A Dhelper.c7486 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) in cpsr_read()
7487 | ((env->condexec_bits & 0xfc) << 8) in cpsr_read()
7507 env->condexec_bits &= ~3; in cpsr_write()
7508 env->condexec_bits |= (val >> 25) & 3; in cpsr_write()
7511 env->condexec_bits &= 3; in cpsr_write()
7512 env->condexec_bits |= (val >> 8) & 0xfc; in cpsr_write()
8077 env->condexec_bits = 0; in take_aarch32_exception()
8444 env->condexec_bits = 0; in arm_cpu_do_interrupt_aarch64()
11427 flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits); in cpu_get_tb_cpu_state()
/dports/emulators/qemu42/qemu-4.2.1/target/arm/
H A Dcpu.h262 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ member
1296 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) in xpsr_read()
1297 | ((env->condexec_bits & 0xfc) << 8) in xpsr_read()
1322 env->condexec_bits &= ~3; in xpsr_write()
1323 env->condexec_bits |= (val >> 25) & 3; in xpsr_write()
1326 env->condexec_bits &= 3; in xpsr_write()
1327 env->condexec_bits |= (val >> 8) & 0xfc; in xpsr_write()
H A Dhelper.c7486 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) in cpsr_read()
7487 | ((env->condexec_bits & 0xfc) << 8) in cpsr_read()
7507 env->condexec_bits &= ~3; in cpsr_write()
7508 env->condexec_bits |= (val >> 25) & 3; in cpsr_write()
7511 env->condexec_bits &= 3; in cpsr_write()
7512 env->condexec_bits |= (val >> 8) & 0xfc; in cpsr_write()
8077 env->condexec_bits = 0; in take_aarch32_exception()
8444 env->condexec_bits = 0; in arm_cpu_do_interrupt_aarch64()
11427 flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits); in cpu_get_tb_cpu_state()
/dports/emulators/qemu5/qemu-5.2.0/target/arm/
H A Dcpu.h274 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ member
1377 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) in xpsr_read()
1378 | ((env->condexec_bits & 0xfc) << 8) in xpsr_read()
1403 env->condexec_bits &= ~3; in xpsr_write()
1404 env->condexec_bits |= (val >> 25) & 3; in xpsr_write()
1407 env->condexec_bits &= 3; in xpsr_write()
1408 env->condexec_bits |= (val >> 8) & 0xfc; in xpsr_write()
H A Dhelper.c8743 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) in cpsr_read()
8744 | ((env->condexec_bits & 0xfc) << 8) in cpsr_read()
8764 env->condexec_bits &= ~3; in cpsr_write()
8765 env->condexec_bits |= (val >> 25) & 3; in cpsr_write()
8768 env->condexec_bits &= 3; in cpsr_write()
8769 env->condexec_bits |= (val >> 8) & 0xfc; in cpsr_write()
9343 env->condexec_bits = 0; in take_aarch32_exception()
9823 env->condexec_bits = 0; in arm_cpu_do_interrupt_aarch64()
13085 flags = FIELD_DP32(flags, TBFLAG_AM32, CONDEXEC, env->condexec_bits); in cpu_get_tb_cpu_state()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/arm/
H A Dcpu.h269 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ member
1344 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) in xpsr_read()
1345 | ((env->condexec_bits & 0xfc) << 8) in xpsr_read()
1370 env->condexec_bits &= ~3; in xpsr_write()
1371 env->condexec_bits |= (val >> 25) & 3; in xpsr_write()
1374 env->condexec_bits &= 3; in xpsr_write()
1375 env->condexec_bits |= (val >> 8) & 0xfc; in xpsr_write()
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/arm/
H A Dcpu.h269 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ member
1344 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) in xpsr_read()
1345 | ((env->condexec_bits & 0xfc) << 8) in xpsr_read()
1370 env->condexec_bits &= ~3; in xpsr_write()
1371 env->condexec_bits |= (val >> 25) & 3; in xpsr_write()
1374 env->condexec_bits &= 3; in xpsr_write()
1375 env->condexec_bits |= (val >> 8) & 0xfc; in xpsr_write()
/dports/emulators/qemu60/qemu-6.0.0/target/arm/
H A Dcpu.h281 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ member
1397 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) in xpsr_read()
1398 | ((env->condexec_bits & 0xfc) << 8) in xpsr_read()
1423 env->condexec_bits &= ~3; in xpsr_write()
1424 env->condexec_bits |= (val >> 25) & 3; in xpsr_write()
1427 env->condexec_bits &= 3; in xpsr_write()
1428 env->condexec_bits |= (val >> 8) & 0xfc; in xpsr_write()
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/arm/
H A Dcpu.h287 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ member
1415 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) in xpsr_read()
1416 | ((env->condexec_bits & 0xfc) << 8) in xpsr_read()
1441 env->condexec_bits &= ~3; in xpsr_write()
1442 env->condexec_bits |= (val >> 25) & 3; in xpsr_write()
1445 env->condexec_bits &= 3; in xpsr_write()
1446 env->condexec_bits |= (val >> 8) & 0xfc; in xpsr_write()
H A Dmve_helper.c39 if ((env->condexec_bits & 0xf) != 0) { in mve_eci_mask()
43 eci = env->condexec_bits >> 4; in mve_eci_mask()
117 if ((env->condexec_bits & 0xf) == 0) { in mve_advance_vpt()
118 env->condexec_bits = (env->condexec_bits == (ECI_A0A1A2B0 << 4)) ? in mve_advance_vpt()
H A Dtranslate.c392 store_cpu_field(tmp, condexec_bits); in clear_eci_state()
769 store_cpu_field(tmp, condexec_bits); in gen_set_condexec()
9517 store_cpu_field(tmp, condexec_bits); in arm_tr_tb_start()
9529 uint32_t condexec_bits; in arm_tr_insn_start() local
9532 condexec_bits = dc->eci << 4; in arm_tr_insn_start()
9534 condexec_bits = (dc->condexec_cond << 4) | (dc->condexec_mask >> 1); in arm_tr_insn_start()
9536 tcg_gen_insn_start(dc->base.pc_next, condexec_bits, 0); in arm_tr_insn_start()
9951 env->condexec_bits = 0; in restore_state_to_opc()
9955 env->condexec_bits = data[1]; in restore_state_to_opc()
/dports/emulators/qemu/qemu-6.2.0/target/arm/
H A Dcpu.h287 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ member
1415 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) in xpsr_read()
1416 | ((env->condexec_bits & 0xfc) << 8) in xpsr_read()
1441 env->condexec_bits &= ~3; in xpsr_write()
1442 env->condexec_bits |= (val >> 25) & 3; in xpsr_write()
1445 env->condexec_bits &= 3; in xpsr_write()
1446 env->condexec_bits |= (val >> 8) & 0xfc; in xpsr_write()
H A Dmve_helper.c39 if ((env->condexec_bits & 0xf) != 0) { in mve_eci_mask()
43 eci = env->condexec_bits >> 4; in mve_eci_mask()
117 if ((env->condexec_bits & 0xf) == 0) { in mve_advance_vpt()
118 env->condexec_bits = (env->condexec_bits == (ECI_A0A1A2B0 << 4)) ? in mve_advance_vpt()
H A Dtranslate.c367 store_cpu_field_constant(0, condexec_bits); in clear_eci_state()
742 store_cpu_field_constant(val, condexec_bits); in gen_set_condexec()
9482 store_cpu_field_constant(0, condexec_bits); in arm_tr_tb_start()
9494 uint32_t condexec_bits; in arm_tr_insn_start() local
9497 condexec_bits = dc->eci << 4; in arm_tr_insn_start()
9499 condexec_bits = (dc->condexec_cond << 4) | (dc->condexec_mask >> 1); in arm_tr_insn_start()
9501 tcg_gen_insn_start(dc->base.pc_next, condexec_bits, 0); in arm_tr_insn_start()
9916 env->condexec_bits = 0; in restore_state_to_opc()
9920 env->condexec_bits = data[1]; in restore_state_to_opc()

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