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Searched refs:db_gpio_out (Results 1 – 10 of 10) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/
H A Dn3xx_db_fe_core.v27 …input [31:0] db_gpio_in, output [31:0] db_gpio_out, output [31:0] db_gpio_ddr, input [31:0] db_gpi… port
45 ….db_gpio_in(db_gpio_in), .db_gpio_out(db_gpio_out), .db_gpio_ddr(db_gpio_ddr), .db_gpio_fab(db_gpi…
H A Dn3xx_core.v912 wire [15:0] db_gpio_out[0:NUM_CHANNELS-1]; net
935 assign db_gpio_out_flat[16*i+15:16*i] = db_gpio_out[i];
993 .db_gpio_out(db_gpio_out[i]),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e31x/
H A De31x_core.v475 wire [DB_GPIO_WIDTH-1:0] db_gpio_out[0:NUM_CHANNELS-1]; net
525 ….db_gpio_in(db_gpio_in[i]), .db_gpio_out(db_gpio_out[i]), .db_gpio_ddr(db_gpio_ddr[i]), .db_gpio_f…
538 assign db_gpio_out_flat[DB_GPIO_WIDTH*i +: DB_GPIO_WIDTH] = db_gpio_out[i];
H A De31x.v734 wire [DB_GPIO_WIDTH-1:0] db_gpio_out[0:NUM_CHANNELS-1]; net
744 assign db_gpio_out[i] = db_gpio_out_flat[DB_GPIO_WIDTH*i +: DB_GPIO_WIDTH];
754 .gpio_out(db_gpio_out[i]),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/control/
H A Ddb_control.v24 …input [31:0] db_gpio_in, output [31:0] db_gpio_out, output [31:0] db_gpio_ddr, input [31:0] db_gpi… port
87 .gpio_in(db_gpio_in), .gpio_out(db_gpio_out), .gpio_ddr(db_gpio_ddr),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/
H A Dx300_core.v531 …wire [31:0] db_gpio_in[0:NUM_DBOARDS-1], db_gpio_out[0:NUM_DBOARDS-1], db_gpio_ddr[0:NUM_DBOARDS-1… net
576 ….db_gpio_in(db_gpio_in[i]), .db_gpio_out(db_gpio_out[i]), .db_gpio_ddr(db_gpio_ddr[i]), .db_gpio_f…
683 assign db0_gpio_out = db_gpio_out[0];
684 assign db1_gpio_out = db_gpio_out[1];
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/dboards/rh/
H A Dn3xx.v3324 wire [16*NUM_CHANNELS-1:0] db_gpio_out; net
3346 assign DBA_TXRX_SW_CTRL_1 = db_gpio_out[16*0+0];
3347 assign DBA_TXRX_SW_CTRL_2 = db_gpio_out[16*0+1];
3348 assign DBA_LED_RX = db_gpio_out[16*0+2];
3349 assign DBA_LED_RX2 = db_gpio_out[16*0+3];
3350 assign DBA_LED_TX = db_gpio_out[16*0+4];
3370 assign DBB_TXRX_SW_CTRL_1 = db_gpio_out[16*1+0];
3372 assign DBB_LED_RX = db_gpio_out[16*1+2];
3373 assign DBB_LED_RX2 = db_gpio_out[16*1+3];
3374 assign DBB_LED_TX = db_gpio_out[16*1+4];
[all …]
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e320/
H A De320_core.v831 wire [DB_GPIO_WIDTH-1:0] db_gpio_out[0:NUM_CHANNELS-1]; net
881 ….db_gpio_in(db_gpio_in[i]), .db_gpio_out(db_gpio_out[i]), .db_gpio_ddr(db_gpio_ddr[i]), .db_gpio_f…
894 assign db_gpio_out_flat[DB_GPIO_WIDTH*i +: DB_GPIO_WIDTH] = db_gpio_out[i];
H A De320.v736 wire [DB_GPIO_WIDTH-1:0] db_gpio_out[0:NUM_CHANNELS-1]; net
745 assign db_gpio_out[i] = db_gpio_out_flat[DB_GPIO_WIDTH*i +: DB_GPIO_WIDTH];
755 .gpio_out(db_gpio_out[i]),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/dboards/mg/
H A Dn3xx.v3352 wire [16*NUM_CHANNELS-1:0] db_gpio_out; net
3393 dsa_tx1_a_out_iob <= db_gpio_out[16*0+11:16*0+6];
3394 dsa_rx1_a_out_iob <= db_gpio_out[16*0+5:16*0+0];
3395 dsa_tx2_a_out_iob <= db_gpio_out[16*1+11:16*1+6];
3396 dsa_rx2_a_out_iob <= db_gpio_out[16*1+5:16*1+0];
3457 dsa_tx1_b_out_iob <= db_gpio_out[16*2+11:16*2+6];
3458 dsa_rx1_b_out_iob <= db_gpio_out[16*2+5:16*2+0];
3459 dsa_tx2_b_out_iob <= db_gpio_out[16*3+11:16*3+6];
3460 dsa_rx2_b_out_iob <= db_gpio_out[16*3+5:16*3+0];
3584 .db_gpio_out_flat(db_gpio_out),