| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/control/ |
| H A D | ram_2port.v | 64 input wire wea, port
83 .clka(clka), .ena(ena), .wea(wea), .addra(addra), .dia(dia), .doa(doa),
91 .clka(clka), .ena(ena), .wea(wea), .addra(addra), .dia(dia), .doa(doa),
99 .clka(clka), .ena(ena), .wea(wea), .addra(addra), .dia(dia), .doa(doa),
107 .clka(clka), .ena(ena), .wea(wea), .addra(addra), .dia(dia), .doa(doa),
115 .clka(clka), .ena(ena), .wea(wea), .addra(addra), .dia(dia), .doa(doa),
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| H A D | ram_2port_impl.vh | 19 input wire wea, port
71 if (wea)
88 if (wea) begin
112 if (wea)
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| /dports/cad/yosys/yosys-yosys-0.12/techlibs/gatemate/ |
| H A D | cells_sim.v | 657 wire wea = A_WE_INV ^ A_WE; net
737 if (enb && !wea) A_DO_out[k] <= memory[addrb+k];
740 if (enb && !wea) B_DO_out[k-20] <= memory[addrb+k];
750 if (ena && wea && A_BM[i]) memory[addra+i] <= A_DI[i];
753 if (ena && !wea) A_DO_out[i] <= memory[addra+i];
757 if (wea && A_BM[i]) begin
1192 wire wea = A_WE_INV ^ A_WE; net
1278 if (enb && !wea) A_DO_out[k] <= memory[addrb+k];
1281 if (enb && !wea) B_DO_out[k-40] <= memory[addrb+k];
1322 if (ena && wea && A_BM[i])
[all …]
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/ |
| H A D | lm32_ram.vhd | 28 signal wea : std_logic; signal
38 wea <= enable_write and write_enable;
48 wea_i => wea,
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/fosphor/ |
| H A D | f15_histo_mem.v | 121 .wea(even_wea),
138 .wea(odd_wea),
158 input wire wea, port
229 assign ramb_wea[i] = onehota[i] & wea;
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/control_lib/ |
| H A D | ram_2port.v | 25 input wea, port
46 if (wea)
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| H A D | double_buffer.v | 69 (.clka(clk),.ena(access_stb & access_ok & (access_ptr == 0)),.wea(access_we),
75 (.clka(clk),.ena(access_stb & access_ok & (access_ptr == 1)),.wea(access_we),
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| H A D | longfifo.v | 58 .wea(write),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/zpu/ |
| H A D | zpu_bootram.v | 54 .wea(ram0_wea),
62 .wea(ram1_wea),
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| /dports/cad/ghdl/ghdl-1.0.0/testsuite/synth/synth111/ |
| H A D | rams_sdp_3d.vhd | 24 wea : in std_logic_vector(NUM_RAMS-1 downto 0); port
42 if(wea(i) = '1') then
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/fifo/ |
| H A D | buffer_int2.v | 170 (.clka(wb_clk_i),.ena(wb_stb_i),.wea(1'b0),
176 (.clka(wb_clk_i),.ena(wb_stb_i),.wea(wb_we_i),
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| H A D | fifo_long.v | 65 .wea(write),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/ |
| H A D | fft_shift.v | 67 .clka(clk),.ena(1'b1),.wea(ping_wr_en),.addra(ping_wr_addr),.dia(i_tdata),.doa(),
74 .clka(clk),.ena(1'b1),.wea(pong_wr_en),.addra(pong_wr_addr),.dia(i_tdata),.doa(),
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| H A D | ram_to_fifo.v | 38 …(.clka(clk), .ena(1'b1), .wea(config_tvalid), .addra(write_addr), .dia(config_tdata), .doa(), // W…
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/wishbone/ |
| H A D | axi_stream_to_wb.v | 119 .clka(clk_i), .ena(rx_tready), .wea(rx_tvalid),
140 .clka(clk_i), .ena(enb_out), .wea(1'b0),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/packet_proc/ |
| H A D | cvita_dest_lookup.v | 26 .clka(clk), .ena(1'b1), .wea(set_stb), .addra(set_addr), .dia(set_data), .doa(),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/packet_proc_200/ |
| H A D | cvita_dest_lookup_legacy.v | 26 .clka(clk), .ena(1'b1), .wea(set_stb), .addra(set_addr), .dia(set_data), .doa(),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/serdes/ |
| H A D | serdes_tb.v | 67 … ram_tx(.clka(clk),.ena(wb_en_tx),.wea(wb_we_tx),.addra(wb_adr),.dia(wb_dat_i),.doa(wb_dat_o_tx),
101 … ram_rx(.clka(clk),.ena(wb_en_rx),.wea(wb_we_rx),.addra(wb_adr),.dia(wb_dat_i),.doa(wb_dat_o_rx),
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| /dports/science/py-pyscf/pyscf-2.0.1/examples/pbc/ |
| H A D | 24-k_points_vs_gamma.py | 40 eea, wea = mycc.eaccsd(nroots=2) variable
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| /dports/cad/yosys/yosys-yosys-0.12/techlibs/anlogic/ |
| H A D | eagle_bb.v | 283 input wea, port
372 input wea, port
975 input wea, port
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/custom/ |
| H A D | power_trig.v | 84 (.clka(clk),.ena(1),.wea(ddc_out_strobe),.addra(wr_addr),.dia(ddc_out_sample),.doa(),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/dsp/ |
| H A D | variable_delay_line.v | 134 .clka (clk), .ena(clk_en), .wea(w_en),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/gpmc/ |
| H A D | fifo_to_gpmc.v | 155 (.clka(clk),.ena(1'b1),.wea(src_rdy_i && dst_rdy_o),
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| H A D | gpmc_to_fifo.v | 160 (.clka(~EM_CLK),.ena(1'b1),.wea(EM_WE),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/fifo/ |
| H A D | axi_fifo_bram.v | 58 .wea(write),
|