| /dragonfly/sys/dev/netif/ath/ath_hal/ar5211/ |
| H A D | ar5211_recv.c | 59 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE); in ar5211EnableReceive()
68 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */ in ar5211StopDmaReceive()
69 if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) { in ar5211StopDmaReceive()
74 , OS_REG_READ(ah, AR_CR) in ar5211StopDmaReceive()
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| H A D | ar5211reg.h | 32 #define AR_CR 0x0008 /* control register */ macro
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| /dragonfly/sys/dev/netif/ath/ath_hal/ar5210/ |
| H A D | ar5210_recv.c | 58 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE); in ar5210EnableReceive()
69 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */ in ar5210StopDmaReceive()
71 if ((OS_REG_READ(ah, AR_CR) & AR_CR_RXE) == 0) in ar5210StopDmaReceive()
77 ath_hal_printf(ah, "AR_CR=0x%x\n", OS_REG_READ(ah, AR_CR)); in ar5210StopDmaReceive()
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| H A D | ar5210_xmit.c | 300 if (OS_REG_READ(ah, AR_CR) & AR_CR_TXE0) in ar5210SetTxDP()
302 __func__, OS_REG_READ(ah, AR_CR)); in ar5210SetTxDP()
378 OS_REG_WRITE(ah, AR_CR, AR_CR_TXE0); in ar5210StartTxDma()
381 OS_REG_WRITE(ah, AR_CR, AR_CR_TXE1); /* enable altq xmit */ in ar5210StartTxDma()
440 OS_REG_WRITE(ah, AR_CR, AR_CR_TXD0); in ar5210StopTxDma()
446 OS_REG_WRITE(ah, AR_CR, 0); in ar5210StopTxDma()
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| H A D | ar5210reg.h | 36 #define AR_CR 0x0008 /* Command register */ macro
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| /dragonfly/sys/contrib/dev/ath/ath_hal/ar9300/ |
| H A D | ar9300_recv.c | 61 OS_REG_WRITE(ah, AR_CR, 0); in ar9300_enable_receive()
138 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); in ar9300_stop_dma_receive()
142 if ((OS_REG_READ(ah, AR_CR) & AR_CR_RXE) == 0) { in ar9300_stop_dma_receive()
153 OS_REG_READ(ah, AR_CR), in ar9300_stop_dma_receive()
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| H A D | ar9300_power.c | 990 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */ in ar9300_set_power_mode_wow_sleep()
991 if (!ath_hal_waitfor(ah, AR_CR, AR_CR_RXE, 0, AH_WAIT_TIMEOUT)) { in ar9300_set_power_mode_wow_sleep()
994 OS_REG_READ(ah, AR_CR), OS_REG_READ(ah, AR_DIAG_SW)); in ar9300_set_power_mode_wow_sleep()
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| H A D | ar9300_tx99_tgt.c | 507 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); // set receive disable in ar9300_tx99_tgt_start()
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| H A D | ar9300_xmit_ds.c | 492 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* set receive disable */ in ar9300__cont_tx_mode()
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| H A D | ar9300_misc.c | 1379 ath_hal_printf(ah, "AR_CR 0x%x \n", OS_REG_READ(ah, AR_CR)); in ar9300_dma_reg_dump()
3810 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* set receive disable */ in ar9300_tx99_start()
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| H A D | ar9300reg.h | 33 #define AR_CR AR_MAC_DMA_OFFSET(MAC_DMA_CR) macro
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| H A D | ar9300_reset.c | 2059 (OS_REG_READ(ah, AR_CR) & AR_CR_RXE)) { in ar9300_chip_reset()
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| /dragonfly/sys/dev/netif/ath/ath_hal/ar5212/ |
| H A D | ar5212_recv.c | 58 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE); in ar5212EnableReceive()
68 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */ in ar5212StopDmaReceive()
69 if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) { in ar5212StopDmaReceive()
75 OS_REG_READ(ah, AR_CR), in ar5212StopDmaReceive()
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| H A D | ar5212reg.h | 27 #define AR_CR 0x0008 /* MAC control register */ macro
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| H A D | ar5212_reset.c | 1142 OS_REG_SET_BIT(ah, AR_CR, AR_CR_RXD); in ar5212MacStop()
1155 if (!OS_REG_IS_BIT_SET(ah, AR_CR, AR_CR_RXE)) { in ar5212MacStop()
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| /dragonfly/sys/dev/netif/ath/ath_hal/ar5416/ |
| H A D | ar5416_recv.c | 78 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */ in ar5416StopDmaReceive()
79 if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) { in ar5416StopDmaReceive()
85 OS_REG_READ(ah, AR_CR), in ar5416StopDmaReceive()
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| /dragonfly/tools/tools/ath/common/ |
| H A D | dumpregs_5210.c | 45 DEFBASICfmt(AR_CR, "CR", AR_CR_BITS),
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| H A D | dumpregs_5211.c | 43 DEFBASICfmt(AR_CR, "CR", AR_CR_BITS),
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| H A D | dumpregs_5212.c | 46 DEFBASIC(AR_CR, "CR"),
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| H A D | dumpregs_5416.c | 45 DEFBASIC(AR_CR, "CR"),
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