Home
last modified time | relevance | path

Searched refs:AR_CR_RXD (Results 1 – 14 of 14) sorted by relevance

/dragonfly/sys/dev/netif/ath/ath_hal/ar5211/
H A Dar5211_recv.c68 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */ in ar5211StopDmaReceive()
H A Dar5211reg.h274 #define AR_CR_RXD 0x00000020 /* Receive disable */ macro
/dragonfly/sys/dev/netif/ath/ath_hal/ar5210/
H A Dar5210reg.h113 #define AR_CR_RXD 0x00000020 /* RX disable */ macro
H A Dar5210_recv.c69 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */ in ar5210StopDmaReceive()
/dragonfly/sys/dev/netif/ath/ath_hal/ar5416/
H A Dar5416_recv.c78 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */ in ar5416StopDmaReceive()
/dragonfly/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_recv.c138 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); in ar9300_stop_dma_receive()
H A Dar9300_tx99_tgt.c507 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); // set receive disable in ar9300_tx99_tgt_start()
H A Dar9300_xmit_ds.c492 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* set receive disable */ in ar9300__cont_tx_mode()
H A Dar9300_power.c990 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */ in ar9300_set_power_mode_wow_sleep()
H A Dar9300reg.h36 #define AR_CR_RXD 0x00000020 // Receive disable macro
H A Dar9300_misc.c3810 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* set receive disable */ in ar9300_tx99_start()
/dragonfly/sys/dev/netif/ath/ath_hal/ar5212/
H A Dar5212_recv.c68 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */ in ar5212StopDmaReceive()
H A Dar5212reg.h340 #define AR_CR_RXD 0x00000020 /* Receive disable */ macro
H A Dar5212_reset.c1142 OS_REG_SET_BIT(ah, AR_CR, AR_CR_RXD); in ar5212MacStop()