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Searched refs:AR_CR_RXE (Results 1 – 12 of 12) sorted by relevance

/dragonfly/sys/dev/netif/ath/ath_hal/ar5211/
H A Dar5211_recv.c59 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE); in ar5211EnableReceive()
69 if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) { in ar5211StopDmaReceive()
H A Dar5211reg.h273 #define AR_CR_RXE 0x00000004 /* Receive enable */ macro
/dragonfly/sys/dev/netif/ath/ath_hal/ar5210/
H A Dar5210_recv.c58 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE); in ar5210EnableReceive()
71 if ((OS_REG_READ(ah, AR_CR) & AR_CR_RXE) == 0) in ar5210StopDmaReceive()
H A Dar5210reg.h110 #define AR_CR_RXE 0x00000004 /* RX enable */ macro
/dragonfly/sys/dev/netif/ath/ath_hal/ar5212/
H A Dar5212_recv.c58 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE); in ar5212EnableReceive()
69 if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) { in ar5212StopDmaReceive()
H A Dar5212reg.h339 #define AR_CR_RXE 0x00000004 /* Receive enable */ macro
H A Dar5212_reset.c1155 if (!OS_REG_IS_BIT_SET(ah, AR_CR, AR_CR_RXE)) { in ar5212MacStop()
/dragonfly/sys/dev/netif/ath/ath_hal/ar5416/
H A Dar5416_recv.c79 if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) { in ar5416StopDmaReceive()
/dragonfly/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_recv.c142 if ((OS_REG_READ(ah, AR_CR) & AR_CR_RXE) == 0) { in ar9300_stop_dma_receive()
H A Dar9300_power.c991 if (!ath_hal_waitfor(ah, AR_CR, AR_CR_RXE, 0, AH_WAIT_TIMEOUT)) { in ar9300_set_power_mode_wow_sleep()
H A Dar9300reg.h38 #define AR_CR_RXE (AR_CR_LP_RXE|AR_CR_HP_RXE) macro
H A Dar9300_reset.c2059 (OS_REG_READ(ah, AR_CR) & AR_CR_RXE)) { in ar9300_chip_reset()