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Searched refs:AR_DIAG_SW (Results 1 – 25 of 31) sorted by relevance

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/dragonfly/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_recv.c72 OS_REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); in ar9300_set_rx_abort()
77 OS_REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); in ar9300_set_rx_abort()
86 OS_REG_CLR_BIT(ah, AR_DIAG_SW, in ar9300_set_rx_abort()
97 OS_REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); in ar9300_set_rx_abort()
154 OS_REG_READ(ah, AR_DIAG_SW)); in ar9300_stop_dma_receive()
179 OS_REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); in ar9300_start_pcu_receive()
188 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS); in ar9300_stop_pcu_receive()
H A Dar9300_tx99_tgt.c505 OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS); in ar9300_tx99_tgt_start()
524 …OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) &~ (AR_DIAG_FORCE_RX_CLEAR | AR_DIAG_IGNO… in ar9300_tx99_tgt_stop()
H A Dar9300_xmit.c670 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); in ar9300_stop_tx_dma()
689 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); in ar9300_stop_tx_dma()
775 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); in ar9300_stop_tx_dma_indv_que()
794 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); in ar9300_stop_tx_dma_indv_que()
854 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH | AR_DIAG_RX_DIS | in ar9300_abort_tx_dma()
915 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH | AR_DIAG_RX_DIS | in ar9300_abort_tx_dma()
H A Dar9300_xmit_ds.c487 OS_REG_WRITE(ah, AR_DIAG_SW, in ar9300__cont_tx_mode()
488 (OS_REG_READ(ah, AR_DIAG_SW) | in ar9300__cont_tx_mode()
554 OS_REG_WRITE(ah, AR_DIAG_SW, in ar9300__cont_tx_mode()
555 (OS_REG_READ(ah, AR_DIAG_SW) & in ar9300__cont_tx_mode()
H A Dar9300_misc.c1003 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg); in ar9300_set_capability()
1881 val = OS_REG_READ(ah, AR_DIAG_SW); in ar9300_get_11n_rx_clear()
1906 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_CTL_LOW); in ar9300_set_11n_rx_clear()
1908 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_CTL_LOW); in ar9300_set_11n_rx_clear()
1912 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_EXT_LOW); in ar9300_set_11n_rx_clear()
1914 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_EXT_LOW); in ar9300_set_11n_rx_clear()
3808 OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS); in ar9300_tx99_start()
3829 OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_RX_DIS); in ar9300_tx99_stop()
H A Dar9300_mci.c535 OS_REG_RMW_FIELD(ah, AR_DIAG_SW, AR_DIAG_OBS_PT_SEL1, 0x03); in ar9300_mci_observation_set_up()
536 OS_REG_RMW_FIELD(ah, AR_DIAG_SW, AR_DIAG_OBS_PT_SEL2, 0x01); in ar9300_mci_observation_set_up()
/dragonfly/sys/dev/netif/ath/ath_hal/ar5211/
H A Dar5211_recv.c75 , OS_REG_READ(ah, AR_DIAG_SW) in ar5211StopDmaReceive()
90 OS_REG_WRITE(ah, AR_DIAG_SW, in ar5211StartPcuReceive()
91 OS_REG_READ(ah, AR_DIAG_SW) & ~(AR_DIAG_SW_DIS_RX)); in ar5211StartPcuReceive()
100 OS_REG_WRITE(ah, AR_DIAG_SW, in ar5211StopPcuReceive()
101 OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_SW_DIS_RX); in ar5211StopPcuReceive()
H A Dar5211reg.h256 #define AR_DIAG_SW 0x8048 /* PCU control register */ macro
H A Dar5211_reset.c358 OS_REG_WRITE(ah, AR_DIAG_SW, in ar5211Reset()
359 OS_REG_READ(ah, AR_DIAG_SW) | AR5311_DIAG_SW_USE_ECO); in ar5211Reset()
539 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg); in ar5211Reset()
H A Dar5211_misc.c657 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg); in ar5211SetCapability()
/dragonfly/sys/dev/netif/ath/ath_hal/ar5212/
H A Dar5212_recv.c76 OS_REG_READ(ah, AR_DIAG_SW)); in ar5212StopDmaReceive()
93 OS_REG_WRITE(ah, AR_DIAG_SW, in ar5212StartPcuReceive()
94 OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS); in ar5212StartPcuReceive()
107 OS_REG_WRITE(ah, AR_DIAG_SW, in ar5212StopPcuReceive()
108 OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_RX_DIS); in ar5212StopPcuReceive()
H A Dar5212_xmit.c646 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_CHAN_IDLE); in ar5212StopTxDma()
666 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_CHAN_IDLE); in ar5212StopTxDma()
H A Dar5212reg.h271 #define AR_DIAG_SW 0x8048 /* MAC PCU control register */ macro
/dragonfly/sys/dev/netif/ath/ath_hal/ar5210/
H A Dar5210_recv.c78 ath_hal_printf(ah, "AR_DIAG_SW=0x%x\n", OS_REG_READ(ah, AR_DIAG_SW)); in ar5210StopDmaReceive()
90 OS_REG_READ(ah, AR_DIAG_SW) & ~(AR_DIAG_SW_DIS_RX)); in ar5210StartPcuReceive()
100 OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_SW_DIS_RX); in ar5210StopPcuReceive()
H A Dar5210reg.h93 #define AR_DIAG_SW 0x8068 /* PCU control */ macro
H A Dar5210_reset.c463 OS_REG_READ(ah, AR_DIAG_SW) | (AR_DIAG_SW_DIS_TX | AR_DIAG_SW_DIS_RX)); in ar5210PerCalibrationN()
560 OS_REG_READ(ah, AR_DIAG_SW) & ~(AR_DIAG_SW_DIS_TX | AR_DIAG_SW_DIS_RX)); in ar5210PerCalibrationN()
H A Dar5210_misc.c702 OS_REG_WRITE(ah, AR_DIAG_SW, val); in ar5210UpdateDiagReg()
/dragonfly/sys/dev/netif/ath/ath_hal/ar5416/
H A Dar5416_recv.c86 OS_REG_READ(ah, AR_DIAG_SW)); in ar5416StopDmaReceive()
119 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); in ar5416StartPcuReceive()
129 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); in ar5416StopPcuReceive()
H A Dar5416_misc.c380 val = OS_REG_READ(ah, AR_DIAG_SW); in ar5416Get11nRxClear()
405 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_CTL_LOW); in ar5416Set11nRxClear()
407 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_CTL_LOW); in ar5416Set11nRxClear()
411 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_EXT_LOW); in ar5416Set11nRxClear()
413 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_EXT_LOW); in ar5416Set11nRxClear()
H A Dar5416_xmit.c93 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_CHAN_IDLE); in ar5416StopTxDma()
110 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_CHAN_IDLE); in ar5416StopTxDma()
/dragonfly/tools/tools/ath/common/
H A Ddumpregs_5210.c97 DEFBASICfmt(AR_DIAG_SW, "DIAG_SW", AR_DIAG_SW_BITS),
H A Ddumpregs_5211.c254 DEFBASICfmt(AR_DIAG_SW, "DIAG_SW", AR_DIAG_SW_BITS),
H A Ddumpregs_5212.c293 DEFBASICfmt(AR_DIAG_SW, "DIAG_SW",
H A Ddumpregs_5416.c326 DEFBASICfmt(AR_DIAG_SW, "DIAG_SW",
/dragonfly/sys/dev/netif/ath/ath_hal/ar5312/
H A Dar5312_reset.c557 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg); in ar5312Reset()

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