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Searched refs:AR_IMR_S1 (Results 1 – 12 of 12) sorted by relevance

/dragonfly/tools/tools/ath/common/
H A Ddumpregs_5211.c69 DEFINT(AR_IMR_S1, "IMR_S1"),
H A Ddumpregs_5212.c82 DEFINT(AR_IMR_S1, "IMR_S1"),
H A Ddumpregs_5416.c85 DEFINT(AR_IMR_S1, "IMR_S1"),
/dragonfly/sys/dev/netif/ath/ath_hal/ar5211/
H A Dar5211reg.h57 #define AR_IMR_S1 0x00a8 /* Secondary interrupt mask reg 1 */ macro
H A Dar5211_xmit.c186 OS_REG_WRITE(ah, AR_IMR_S1, in setTxQInterrupts()
H A Dar5211_reset.c494 OS_REG_WRITE(ah, AR_IMR_S1, (AR_IMR_S1_QCU_TXERR & AR_QCU_0)); in ar5211Reset()
/dragonfly/sys/dev/netif/ath/ath_hal/ar5212/
H A Dar5212reg.h54 #define AR_IMR_S1 0x00a8 /* MAC Secondary interrupt mask register 1 */ macro
H A Dar5212_xmit.c219 OS_REG_WRITE(ah, AR_IMR_S1, in setTxQInterrupts()
/dragonfly/tools/tools/ath/athregs/
H A Ddumpregs.c517 , OS_REG_READ(ah, AR_IMR_S1) in ath_hal_dumpint()
/dragonfly/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_xmit.c236 OS_REG_WRITE(ah, AR_IMR_S1, in set_tx_q_interrupts()
H A Dar9300reg.h359 #define AR_IMR_S1 AR_MAC_DMA_OFFSET(MAC_DMA_IMR_S1) macro
/dragonfly/sys/dev/netif/ath/ath_hal/ar5416/
H A Dar5416_xmit.c1224 OS_REG_WRITE(ah, AR_IMR_S1, in setTxQInterrupts()