| /dragonfly/sys/dev/netif/ath/ath_hal/ar5212/ |
| H A D | ar5212_interrupts.c | 191 OS_REG_WRITE(ah, AR_IMR_S2, in ar5212SetInterrupts()
192 (OS_REG_READ(ah, AR_IMR_S2) &~ AR_IMR_SR2_BCNMISC) | mask2); in ar5212SetInterrupts()
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| H A D | ar5212reg.h | 55 #define AR_IMR_S2 0x00ac /* MAC Secondary interrupt mask register 2 */ macro
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| H A D | ar5212_xmit.c | 223 OS_REG_RMW_FIELD(ah, AR_IMR_S2, in setTxQInterrupts()
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| H A D | ar5212_reset.c | 577 OS_REG_WRITE(ah, AR_IMR_S2, in ar5212Reset()
578 OS_REG_READ(ah, AR_IMR_S2) in ar5212Reset()
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| /dragonfly/sys/dev/netif/ath/ath_hal/ar5416/ |
| H A D | ar5416_interrupts.c | 343 mask = OS_REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM | in ar5416SetInterrupts()
351 OS_REG_WRITE(ah, AR_IMR_S2, mask | mask2); in ar5416SetInterrupts()
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| H A D | ar5416_reset.c | 697 OS_REG_WRITE(ah, AR_IMR_S2, in ar5416InitIMR()
698 OS_REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT | AR_IMR_S2_CST); in ar5416InitIMR()
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| H A D | ar5416_xmit.c | 1228 OS_REG_RMW_FIELD(ah, AR_IMR_S2, in setTxQInterrupts()
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| /dragonfly/sys/dev/netif/ath/ath_hal/ar5312/ |
| H A D | ar5312_reset.c | 501 OS_REG_WRITE(ah, AR_IMR_S2, in ar5312Reset()
502 OS_REG_READ(ah, AR_IMR_S2) in ar5312Reset()
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| /dragonfly/tools/tools/ath/common/ |
| H A D | dumpregs_5211.c | 70 DEFINT(AR_IMR_S2, "IMR_S2"),
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| H A D | dumpregs_5212.c | 83 DEFINTfmt(AR_IMR_S2, "IMR_S2",
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| H A D | dumpregs_5416.c | 86 DEFINTfmt(AR_IMR_S2, "IMR_S2",
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| /dragonfly/sys/contrib/dev/ath/ath_hal/ar9300/ |
| H A D | ar9300_xmit.c | 240 AR_IMR_S2, AR_IMR_S2_QCU_TXURN, ahp->ah_tx_urn_interrupt_mask); in set_tx_q_interrupts()
241 ahp->ah_mask2Reg = OS_REG_READ(ah, AR_IMR_S2); in set_tx_q_interrupts()
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| H A D | ar9300_interrupts.c | 645 OS_REG_WRITE(ah, AR_IMR_S2, ahp->ah_mask2Reg );
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| H A D | ar9300_reset.c | 4155 OS_REG_WRITE(ah, AR_IMR_S2, OS_REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT); in ar9300_init_interrupt_masks()
4156 ahp->ah_mask2Reg = OS_REG_READ(ah, AR_IMR_S2); in ar9300_init_interrupt_masks()
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| H A D | ar9300reg.h | 366 #define AR_IMR_S2 AR_MAC_DMA_OFFSET(MAC_DMA_IMR_S2) macro
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| /dragonfly/sys/dev/netif/ath/ath_hal/ar5211/ |
| H A D | ar5211reg.h | 58 #define AR_IMR_S2 0x00ac /* Secondary interrupt mask reg 2 */ macro
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| H A D | ar5211_reset.c | 495 OS_REG_WRITE(ah, AR_IMR_S2, (AR_IMR_S2_QCU_TXURN & AR_QCU_0)); in ar5211Reset()
508 OS_REG_WRITE(ah, AR_IMR_S2, OS_REG_READ(ah, AR_IMR_S2) | in ar5211Reset()
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| H A D | ar5211_xmit.c | 190 OS_REG_RMW_FIELD(ah, AR_IMR_S2, in setTxQInterrupts()
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| /dragonfly/tools/tools/ath/athregs/ |
| H A D | dumpregs.c | 518 , OS_REG_READ(ah, AR_IMR_S2) in ath_hal_dumpint()
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