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Searched refs:AR_PHY_AGC_CONTROL (Results 1 – 14 of 14) sorted by relevance

/dragonfly/sys/dev/netif/ath/ath_hal/ar9002/
H A Dar9287_cal.c55 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); in ar9287InitCalHardware()
58 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL, in ar9287InitCalHardware()
59 OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL); in ar9287InitCalHardware()
62 if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, in ar9287InitCalHardware()
70 OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); in ar9287InitCalHardware()
H A Dar9285_cal.c171 OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ar9285_hw_cl_cal()
174 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); in ar9285_hw_cl_cal()
175 if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, in ar9285_hw_cl_cal()
186 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); in ar9285_hw_cl_cal()
188 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); in ar9285_hw_cl_cal()
189 if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, in ar9285_hw_cl_cal()
198 OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); in ar9285_hw_cl_cal()
/dragonfly/sys/dev/netif/ath/ath_hal/ar5416/
H A Dar5416_cal.c211 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, in ar5416InitCalHardware()
216 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); in ar5416InitCalHardware()
219 if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) { in ar5416InitCalHardware()
232 OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ar5416InitCalHardware()
270 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); in ar5416InitCal()
574 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); in ar5416StartNFCal()
575 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); in ar5416StartNFCal()
576 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); in ar5416StartNFCal()
640 OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); in ar5416LoadNF()
642 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); in ar5416LoadNF()
[all …]
/dragonfly/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_reset.c610 if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { in ar9300_store_new_nf()
2264 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); in ar9300_load_nf()
2292 __func__, OS_REG_READ(ah, AR_PHY_AGC_CONTROL)); in ar9300_load_nf()
2373 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); in ar9300_start_nf_cal()
3700 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL, in ar9300_init_cal_internal()
3705 AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0); in ar9300_init_cal_internal()
3723 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL, in ar9300_init_cal_internal()
3737 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL, in ar9300_init_cal_internal()
3741 if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, in ar9300_init_cal_internal()
3810 clc_success = (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & in ar9300_init_cal_internal()
[all …]
H A Dar9300_spectral.c565 if ( (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) == 0) { in ar9300_get_ctl_chan_nf()
585 if ((OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) == 0) { in ar9300_get_ext_chan_nf()
H A Dar9300phy.h557 #define AR_PHY_AGC_CONTROL AR_SM_OFFSET(BB_agc_control) macro
/dragonfly/sys/dev/netif/ath/ath_hal/ar5211/
H A Dar5211_reset.c463 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL, in ar5211Reset()
464 OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL); in ar5211Reset()
465 (void) ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0); in ar5211Reset()
851 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL, in ar5211RunNoiseFloor()
852 OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_NF); in ar5211RunNoiseFloor()
871 if ((OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) == 0) in ar5211RunNoiseFloor()
881 OS_REG_READ(ah, AR_PHY_AGC_CONTROL)); in ar5211RunNoiseFloor()
928 if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { in ar5211IsNfGood()
989 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL, in ar5211CalNoiseFloor()
990 OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | in ar5211CalNoiseFloor()
H A Dar5211phy.h40 #define AR_PHY_AGC_CONTROL 0x9860 /* PHY chip calibration and noise floor setting */ macro
/dragonfly/sys/dev/netif/ath/ath_hal/ar5212/
H A Dar5212_reset.c536 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL, in ar5212Reset()
537 OS_REG_READ(ah, AR_PHY_AGC_CONTROL) in ar5212Reset()
584 if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) { in ar5212Reset()
797 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); in ar5212ChannelChange()
1399 if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { in ar5212GetNf()
1452 OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); in ar5212GetNf()
1454 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); in ar5212GetNf()
1456 if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF, 0)) { in ar5212GetNf()
1459 __func__, OS_REG_READ(ah, AR_PHY_AGC_CONTROL)); in ar5212GetNf()
1470 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); in ar5212GetNf()
[all …]
H A Dar5212phy.h112 #define AR_PHY_AGC_CONTROL 0x9860 /* chip calibration and noise floor setting */ macro
H A Dar5212_misc.c1137 if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) in ar5212IsNFCalInProgress()
/dragonfly/sys/dev/netif/ath/ath_hal/ar5312/
H A Dar5312_reset.c460 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL, in ar5312Reset()
461 OS_REG_READ(ah, AR_PHY_AGC_CONTROL) in ar5312Reset()
508 if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) { in ar5312Reset()
/dragonfly/tools/tools/ath/common/
H A Ddumpregs_5211.c271 DEFVOID(AR_PHY_AGC_CONTROL, "PHY_AGC_CONTROL"),
H A Ddumpregs_5212.c359 DEFVOIDfmt(AR_PHY_AGC_CONTROL, "PHY_AGC_CONTROL",