/dragonfly/sys/dev/netif/ath/ath_hal/ar9002/ |
H A D | ar9287_cal.c | 55 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); in ar9287InitCalHardware() 58 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL, in ar9287InitCalHardware() 59 OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL); in ar9287InitCalHardware() 62 if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, in ar9287InitCalHardware() 70 OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); in ar9287InitCalHardware()
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H A D | ar9285_cal.c | 171 OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ar9285_hw_cl_cal() 174 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); in ar9285_hw_cl_cal() 175 if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, in ar9285_hw_cl_cal() 186 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); in ar9285_hw_cl_cal() 188 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); in ar9285_hw_cl_cal() 189 if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, in ar9285_hw_cl_cal() 198 OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); in ar9285_hw_cl_cal()
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/dragonfly/sys/dev/netif/ath/ath_hal/ar5416/ |
H A D | ar5416_cal.c | 211 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, in ar5416InitCalHardware() 216 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); in ar5416InitCalHardware() 219 if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) { in ar5416InitCalHardware() 232 OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ar5416InitCalHardware() 270 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); in ar5416InitCal() 574 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); in ar5416StartNFCal() 575 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); in ar5416StartNFCal() 576 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); in ar5416StartNFCal() 640 OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); in ar5416LoadNF() 642 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); in ar5416LoadNF() [all …]
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/dragonfly/sys/contrib/dev/ath/ath_hal/ar9300/ |
H A D | ar9300_reset.c | 610 if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { in ar9300_store_new_nf() 2264 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); in ar9300_load_nf() 2292 __func__, OS_REG_READ(ah, AR_PHY_AGC_CONTROL)); in ar9300_load_nf() 2373 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); in ar9300_start_nf_cal() 3700 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL, in ar9300_init_cal_internal() 3705 AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0); in ar9300_init_cal_internal() 3723 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL, in ar9300_init_cal_internal() 3737 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL, in ar9300_init_cal_internal() 3741 if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, in ar9300_init_cal_internal() 3810 clc_success = (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & in ar9300_init_cal_internal() [all …]
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H A D | ar9300_spectral.c | 565 if ( (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) == 0) { in ar9300_get_ctl_chan_nf() 585 if ((OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) == 0) { in ar9300_get_ext_chan_nf()
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H A D | ar9300phy.h | 557 #define AR_PHY_AGC_CONTROL AR_SM_OFFSET(BB_agc_control) macro
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/dragonfly/sys/dev/netif/ath/ath_hal/ar5211/ |
H A D | ar5211_reset.c | 463 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL, in ar5211Reset() 464 OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL); in ar5211Reset() 465 (void) ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0); in ar5211Reset() 851 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL, in ar5211RunNoiseFloor() 852 OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_NF); in ar5211RunNoiseFloor() 871 if ((OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) == 0) in ar5211RunNoiseFloor() 881 OS_REG_READ(ah, AR_PHY_AGC_CONTROL)); in ar5211RunNoiseFloor() 928 if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { in ar5211IsNfGood() 989 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL, in ar5211CalNoiseFloor() 990 OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | in ar5211CalNoiseFloor()
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H A D | ar5211phy.h | 40 #define AR_PHY_AGC_CONTROL 0x9860 /* PHY chip calibration and noise floor setting */ macro
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/dragonfly/sys/dev/netif/ath/ath_hal/ar5212/ |
H A D | ar5212_reset.c | 536 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL, in ar5212Reset() 537 OS_REG_READ(ah, AR_PHY_AGC_CONTROL) in ar5212Reset() 584 if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) { in ar5212Reset() 797 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); in ar5212ChannelChange() 1399 if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { in ar5212GetNf() 1452 OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); in ar5212GetNf() 1454 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); in ar5212GetNf() 1456 if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF, 0)) { in ar5212GetNf() 1459 __func__, OS_REG_READ(ah, AR_PHY_AGC_CONTROL)); in ar5212GetNf() 1470 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); in ar5212GetNf() [all …]
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H A D | ar5212phy.h | 112 #define AR_PHY_AGC_CONTROL 0x9860 /* chip calibration and noise floor setting */ macro
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H A D | ar5212_misc.c | 1137 if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) in ar5212IsNFCalInProgress()
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/dragonfly/sys/dev/netif/ath/ath_hal/ar5312/ |
H A D | ar5312_reset.c | 460 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL, in ar5312Reset() 461 OS_REG_READ(ah, AR_PHY_AGC_CONTROL) in ar5312Reset() 508 if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) { in ar5312Reset()
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/dragonfly/tools/tools/ath/common/ |
H A D | dumpregs_5211.c | 271 DEFVOID(AR_PHY_AGC_CONTROL, "PHY_AGC_CONTROL"),
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H A D | dumpregs_5212.c | 359 DEFVOIDfmt(AR_PHY_AGC_CONTROL, "PHY_AGC_CONTROL",
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