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Searched refs:CG_SPLL_FUNC_CNTL_2 (Results 1 – 20 of 20) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Drv740d.h34 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
H A Drv730d.h37 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
H A Drv770.c1138 tmp = RREG32(CG_SPLL_FUNC_CNTL_2); in rv770_set_clk_bypass_mode()
1141 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in rv770_set_clk_bypass_mode()
1150 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in rv770_set_clk_bypass_mode()
H A Drv740_dpm.c292 RREG32(CG_SPLL_FUNC_CNTL_2); in rv740_read_clock_registers()
H A Drv730_dpm.c205 RREG32(CG_SPLL_FUNC_CNTL_2); in rv730_read_clock_registers()
H A Drv770d.h100 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
H A Dnid.h547 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
H A Dsid.h94 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
H A Dcikd.h257 #define CG_SPLL_FUNC_CNTL_2 0xC0500144 macro
H A Dsi.c3981 tmp = RREG32(CG_SPLL_FUNC_CNTL_2); in si_set_clk_bypass_mode()
3983 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in si_set_clk_bypass_mode()
3991 tmp = RREG32(CG_SPLL_FUNC_CNTL_2); in si_set_clk_bypass_mode()
3993 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in si_set_clk_bypass_mode()
H A Devergreend.h82 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
H A Drv770_dpm.c1528 RREG32(CG_SPLL_FUNC_CNTL_2); in rv770_read_clock_registers()
H A Dni_dpm.c1184 ni_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); in ni_read_clock_registers()
H A Dci_dpm.c1911 RREG32_SMC(CG_SPLL_FUNC_CNTL_2); in ci_read_clock_registers()
H A Dsi_dpm.c3571 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); in si_read_clock_registers()
/dragonfly/sys/dev/drm/amd/powerplay/smumgr/
H A Dfiji_smumgr.c1360 spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, CG_SPLL_FUNC_CNTL_2, in fiji_populate_smc_acpi_level()
H A Diceland_smumgr.c1465 CG_SPLL_FUNC_CNTL_2, SCLK_MUX_SEL, 4); in iceland_populate_smc_acpi_level()
H A Dci_smumgr.c1417 CG_SPLL_FUNC_CNTL_2, SCLK_MUX_SEL, 4); in ci_populate_smc_acpi_level()
H A Dtonga_smumgr.c1204 spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, CG_SPLL_FUNC_CNTL_2, in tonga_populate_smc_acpi_level()
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dsi_dpm.c4031 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); in si_read_clock_registers()