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Searched refs:ENABLE_L1_FRAGMENT_PROCESSING (Results 1 – 14 of 14) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dgmc_v7_0.c617 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); in gmc_v7_0_gart_enable()
738 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); in gmc_v7_0_gart_disable()
H A Dgmc_v8_0.c844 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); in gmc_v8_0_gart_enable()
982 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); in gmc_v8_0_gart_disable()
/dragonfly/sys/dev/drm/radeon/
H A Drv770.c909 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in rv770_pcie_gart_enable()
986 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in rv770_agp_enable()
H A Drv770d.h466 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) macro
H A Dni.c1298 ENABLE_L1_FRAGMENT_PROCESSING | in cayman_pcie_gart_enable()
1380 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING | in cayman_pcie_gart_disable()
H A Dnid.h180 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) macro
H A Dsid.h476 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) macro
H A Dcikd.h601 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) macro
H A Devergreend.h956 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) macro
H A Dr600d.h333 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) macro
H A Dr600.c1139 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in r600_pcie_gart_enable()
1231 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in r600_agp_enable()
H A Devergreen.c2398 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in evergreen_pcie_gart_enable()
2481 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in evergreen_agp_enable()
H A Dsi.c4286 ENABLE_L1_FRAGMENT_PROCESSING | in si_pcie_gart_enable()
H A Dcik.c5469 ENABLE_L1_FRAGMENT_PROCESSING | in cik_pcie_gart_enable()