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Searched refs:ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (Results 1 – 14 of 14) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Drv770.c904 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in rv770_pcie_gart_enable()
981 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in rv770_agp_enable()
H A Drv770d.h645 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) macro
H A Dni.c1305 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in cayman_pcie_gart_enable()
1384 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in cayman_pcie_gart_disable()
H A Dnid.h107 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) macro
H A Dsid.h374 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) macro
H A Dcikd.h492 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) macro
H A Devergreend.h1153 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) macro
H A Dr600d.h590 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) macro
H A Dr600.c1134 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in r600_pcie_gart_enable()
1226 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in r600_agp_enable()
H A Devergreen.c2393 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in evergreen_pcie_gart_enable()
2476 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in evergreen_agp_enable()
H A Dsi.c4293 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in si_pcie_gart_enable()
4379 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in si_pcie_gart_disable()
H A Dcik.c5476 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in cik_pcie_gart_enable()
5593 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in cik_pcie_gart_disable()
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dgmc_v7_0.c626 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v7_0_gart_enable()
H A Dgmc_v8_0.c853 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v8_0_gart_enable()