Searched refs:ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (Results 1 – 14 of 14) sorted by relevance
904 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in rv770_pcie_gart_enable()981 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in rv770_agp_enable()
645 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) macro
1305 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in cayman_pcie_gart_enable()1384 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in cayman_pcie_gart_disable()
107 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) macro
374 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) macro
492 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) macro
1153 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) macro
590 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) macro
1134 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in r600_pcie_gart_enable()1226 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in r600_agp_enable()
2393 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in evergreen_pcie_gart_enable()2476 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in evergreen_agp_enable()
4293 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in si_pcie_gart_enable()4379 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in si_pcie_gart_disable()
5476 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in cik_pcie_gart_enable()5593 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in cik_pcie_gart_disable()
626 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v7_0_gart_enable()
853 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v8_0_gart_enable()